Analog-to-digital converters

Claim 2

An analog-to-digital converter comprising: integrating means, a source of clock pulses, a source of reference signal poled relative to an analog signal supplied to said integrating means for integration thereby, so as to reverse the sign of the slope of the waveform produced at the integrating means output in response to the analog signal applied to the integrating means input, means for counting the clock pulses to measure a time period during which the analog signal is integrated by said integrating means, and means responsive to the pulse counting means for applying said reference signal to the input of said integrating means for integration for a variable time interval which includes a fixed time interval to provide at least a predetermined time integral of the reference signal, the pulse counting means also measuring the interval during which said reference signal is integrated by sAid integrating means to provide a digital representation of the analog signal magnitude, means applying an offset signal of predetermined value to the input of said integrating means for at least part of said time period to provide a predetermined time integral of offset signal integration proportional to the predetermined time integral of the reference signal whereby said digital representation by said counting means is that of said analog signal magnitude independent of said offset signal.

Claim 3

Electrical signal conversion apparatus comprising: integrating means, first, second and third sources of electrical signals, first means for feeding the first signal to said integrating means for a first fixed time interval, second means operative to selectively feed the second signal to said integrating means in a sense opposite that of the first signal, timing means for operating said second means to feed said second signal to said integrating means for at least a second fixed time interval and for timing the interval of second signal integration to provide a time representation of the first signal magnitude, third means for feeding the third signal having a predetermined value to said integrating means for a third fixed time interval at least part of which precedes the integration of said second signal for providing a predetermined signal offset thereto, said second fixed time interval and the value of the third signal being selected so that the time integral of the third signal is proportional to the time integral of the second signal.

Claim 4

Electrical signal conversion apparatus comprising: integrating means, first, second and third sources of electrical signals, first means for feeding the first signal to said integrating means for a first fixed time interval, second means operative to selectively feed the second signal to said integrating means in a sense opposite that of the first signal, timing means for operating said second means to feed said second signal to said integrating means for at least a second fixed time interval and for timing the interval of second signal integration to provide a time representation of the first signal magnitude, third means for feeding the third signal having a predetermined value to said integrating means for a third fixed time interval at least part of which precedes the integration of said second signal for providing a predetermined signal offset thereto, said second fixed time interval and the value of the third signal being selected so that the time integral of the third signal is proportional to the time integral of the second signal.

Claim 5

Apparatus according to claim 2 wherein the polarity of said third signal is the same as the normal polarity of said first signal, and wherein said timing means time advances the operating of said second means relative to said first time interval by said third time interval.

Claim 6

A dual-slope analog-to-digital representation of an analog signal magnitude comprising, a source of reference signal of opposite sense to the input signal, input and reference signal integrating means, a source of clock pulses, a pulse counter drivable by the clock pulses transmitted thereto, start means for initiating the transmission of pulses to the pulse counter, a detector connected to the integrating means for producing an output signal in response to the output potential of the integrating means ramping in one direction to a datum level, a switching device operative in response to a registration by said pulse counter of a predetermined count to terminate a first and fixed time interval during which the integrating means generates a first output potential component which ramps away from said datum level with a slope proportional to the analog signal magnitude and to apply the source of reference signal to said integrating means, said integrating means generating an output potential in response to said reference signal which ramps in said one direction towards said datum level for a second and variable time interval with a slope proportional to the reference signal magnitude, the second time interval being timed by the clock pulses to provide a digital representation of analog signal magnitude, a signal source for applying a second signal to said integrating means at least during the generation of said first output potential component, said integrating means thereby integrating the second signal for said fixed time interval to provide a fixed time interval of said second signal integration, said predetermined count of said counter being equal to the full pulse count capacity of said counter less than the number of pulse counts corresponding to the magnitude of said second signal, said counter including a counting stage for producing an output signal for operating said switching device when said counter registers said predetermined count, whereby said integrating means integrates the reference signal for a fixed time increment of said variable time interval as determined by said number of pulse counts to provide at least a fixed time integral of reference signAl integration which nullifies the time integral of second signal integration, and means coupling said switching device to said counting stage.

Claim 7

A dual-slope analog-to-digital representation of an analog signal magnitude comprising, a source of reference signal of opposite sense to the input signal, input and reference signal integrating means, a source of clock pulses, a pulse counter drivable by the clock pulses transmitted thereto, start means for initiating the transmission of pulses to the pulse counter, a detector connected to the integrating means for producing an output signal in response to the output potential of the integrating means ramping in one direction to a datum level, a switching device operative in response to a registration by said pulse counter of a predetermined count to terminate a first and fixed time interval during which the integrating means generates a first output potential component which ramps away from said datum level with a slope proportional to the analog signal magnitude and to apply the source of reference signal to said integrating means, said integrating means generating an output potential in response to said reference signal which ramps in said one direction towards said datum level for a second and variable time interval with a slope proportional to the reference signal magnitude, the second time interval being timed by the clock pulses to provide a digital representation of analog signal magnitude, a signal source for applying a second signal to said integrating means at least during the generation of said first output potential component, said integrating means thereby integrating the second signal for said fixed time interval to provide a fixed time interval of said second signal integration, said predetermined count of said counter being equal to the full pulse count capacity of said counter less than the number of pulse counts corresponding to the magnitude of said second signal, said counter including a counting stage for producing an output signal for operating said switching device when said counter registers said predetermined count, whereby said integrating means integrates the reference signal for a fixed time increment of said variable time interval as determined by said number of pulse counts to provide at least a fixed time integral of reference signAl integration which nullifies the time integral of second signal integration, and means coupling said switching device to said counting stage.

Claim 8

Apparatus for providing a digital display representative of the magnitude of an analog signal comprising, linear signal integrating means having an input and an output, sources of respective first, second and third analog signals, first means for feeding the first signal to the integrating means input whereby the integrating means output is driven by said first signal in one direction away from a signal level in a first and fixed time interval, second means coupled to the second analog signal source for feeding the second analog signal to the integrating means input in response to a control signal applied to said second means, the second signal having a polarity such as to drive said integrating means output toward said signal level in a second time interval which varies as a function of the first signal magnitude, third means for feeding the third signal to said integrating means input during a second time interval thereby producing a fixed third signal time integral, a pulse counter comprising a plurality of interconnected pulse counting stages one of said counting stages producing said control signal for said second means, a source of clock pulses for driving said counter to time the first and second time intervals, means coupled to said integrating means output and to said counter for providing a digital display representative of the count in said counter when said integrating means output is restored to said signal level, the one counting stage being coupled to said second means and selected so that the counter counts a predetermined number of clock pulses proportional to the time integral of the third signal after producing said control signal to thereby provide a second signal time integral which nullifies the third signal time integral, whereby the digital display is representative of the first signal magnitude exclusive of the magnitude of the third signal when said integrating means output is restored to said signal level.

Claim 9

Apparatus for providing a digital display representative of the magnitude of an analog signal comprising, linear signal integrating means having an input and an output, sources of respective first, second and third analog signals, first means for feeding the first signal to the integrating means input whereby the integrating means output is driven by said first signal in one direction away from a signal level in a first and fixed time interval, second means coupled to the second analog signal source for feeding the second analog signal to the integrating means input in response to a control signal applied to said second means, the second signal having a polarity such as to drive said integrating means output toward said signal level in a second time interval which varies as a function of the first signal magnitude, third means for feeding the third signal to said integrating means input during a second time interval thereby producing a fixed third signal time integral, a pulse counter comprising a plurality of interconnected pulse counting stages one of said counting stages producing said control signal for said second means, a source of clock pulses for driving said counter to time the first and second time intervals, means coupled to said integrating means output and to said counter for providing a digital display representative of the count in said counter when said integrating means output is restored to said signal level, the one counting stage being coupled to said second means and selected so that the counter counts a predetermined number of clock pulses proportional to the time integral of the third signal after producing said control signal to thereby provide a second signal time integral which nullifies the third signal time integral, whereby the digital display is representative of the first signal magnitude exclusive of the magnitude of the third signal when said integrating means output is restored to said signal level.

Claim 10

The apparatus as claimed by claim 5 wherein said third means comprises a conductor connected to said integrating means input for continually feeding said third signal thereto during said first and second time intervals.

Claim 11

An analog-to-digital converter comprising, a source of analog input signal, integrating means for generating at least two sequential output voltage signals of sawtooth waveform relative to a datum signal level during each complete analog-to-digital conversion cycle, each waveform being formed by first and second ramps having slopes of opposite sign, means coupling the analog signal source to said integrating means for at least the total time required to generate the two sawtooth waveforms, means for generating a train of clock pulses having equal time intervals between pulses, pulse counting means including plural intercoupled binary counter stages for producing output binary signals representative of the number of clock pulses received by said counting means, pulse gating means for gating clock pulses from the pulse generating means to said counting means and for blocking the transmission of clock pulses to said counting means in response to a disabling signal applied to said gating means, the frequency of the clock pulses being sufficiently high to drive at least one of said binary counter stages through a series of repetitive counting cycles within the time interval of each first ramp generation, the one counter stage thereby producing a series of pulse signals representing the number of clock pulses received by said counting means during the time interval of each first ramp and producing at least two series of pulse signal during each complete conversion cycle, bistable comparator means having at least two input terminals and an output terminal and two stable states, one of the two comparator means input terminals being coupled to receive the output signals generated By said integrating means, first binary divider means coupling the other comparator means input terminal to said one binary counter stage and producing a divider output signal upon receiving each series of pulse signals from said one counter stage, said comparator means being driven into one of said two stable states by the application thereto of a divider output signal from said first binary divider means and thereby producing at least two sequential first comparator output signals during each complete conversion cycle, means coupled to the output terminal of said comparator means and responsive to each first comparator output signal for coupling to the said integrating means a reference input signal of opposite polarity to the first input signal and of sufficient magnitude to terminate the generation of each first ramp and to initiate the generation of each second ramp, said comparator means being successively driven into the other stable state in response to each second ramp crossing the said datum signal level, said means coupled to the output terminal of said comparator means being additionally responsive to each second comparator output signal for decoupling the reference input signal from said integrating means so as to terminate the generation of each second ramp, and second binary divider means coupled to the output terminal of said comparator means for applying a disabling signal to said gating means upon receiving at least two sequential second comparator output signals so as to automatically terminate said conversion cycle, said pulse counting means thereupon providing an output signal representative of the time integral of the analog signal magnitude.

Claim 12

An analog-to-digital converter comprising, a source of analog input signal, integrating means for generating at least two sequential output voltage signals of sawtooth waveform relative to a datum signal level during each complete analog-to-digital conversion cycle, each waveform being formed by first and second ramps having slopes of opposite sign, means coupling the analog signal source to said integrating means for at least the total time required to generate the two sawtooth waveforms, means for generating a train of clock pulses having equal time intervals between pulses, pulse counting means including plural intercoupled binary counter stages for producing output binary signals representative of the number of clock pulses received by said counting means, pulse gating means for gating clock pulses from the pulse generating means to said counting means and for blocking the transmission of clock pulses to said counting means in response to a disabling signal applied to said gating means, the frequency of the clock pulses being sufficiently high to drive at least one of said binary counter stages through a series of repetitive counting cycles within the time interval of each first ramp generation, the one counter stage thereby producing a series of pulse signals representing the number of clock pulses received by said counting means during the time interval of each first ramp and producing at least two series of pulse signal during each complete conversion cycle, bistable comparator means having at least two input terminals and an output terminal and two stable states, one of the two comparator means input terminals being coupled to receive the output signals generated By said integrating means, first binary divider means coupling the other comparator means input terminal to said one binary counter stage and producing a divider output signal upon receiving each series of pulse signals from said one counter stage, said comparator means being driven into one of said two stable states by the application thereto of a divider output signal from said first binary divider means and thereby producing at least two sequential first comparator output signals during each complete conversion cycle, means coupled to the output terminal of said comparator means and responsive to each first comparator output signal for coupling to the said integrating means a reference input signal of opposite polarity to the first input signal and of sufficient magnitude to terminate the generation of each first ramp and to initiate the generation of each second ramp, said comparator means being successively driven into the other stable state in response to each second ramp crossing the said datum signal level, said means coupled to the output terminal of said comparator means being additionally responsive to each second comparator output signal for decoupling the reference input signal from said integrating means so as to terminate the generation of each second ramp, and second binary divider means coupled to the output terminal of said comparator means for applying a disabling signal to said gating means upon receiving at least two sequential second comparator output signals so as to automatically terminate said conversion cycle, said pulse counting means thereupon providing an output signal representative of the time integral of the analog signal magnitude.

Claim 13

The converter as claimed in claim 7, wherein the first binary divider means comprises at least a divide-by-eight binary divider.

Claim 14

The converter as claimed in claim 8, wherein said second binary divider means comprises a divide-by-four binary divider.

Claim 15

The converter as claimed in claim 7, which further includes means for decoding the output signals of said pulse counting means into decimal-coded output signals, and display means coupled to the decoding means and driven by the decimal-coded output signals to provide a decimal number indication of the analog signal magnitude.

Claim 16

The converter as claimed in claim 10, which further comprises, means for applying a third input signal of constant magnitude to said integrating means, and wherein said one counter stage is selected to advance each pulse signal in time by an interval corresponding to the magnitude of the third signal.