US3713097A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test bit pattern generator for pattern recognition machines
Assignee: International Business Machines Corp
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Filing: 1971-05-14
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Granted: 1973-01-23
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Expires: 1991-05-14
Abstract
Abstract The scanner of the pattern recognition machine scans a preprinted document containing a number of patterns which correspond to the number of test bits to be produced. There are two distinguishing patterns which produce binary one and zero bits. The patterns are printed in a sequence dictated by the desired test bit pattern. The resulting binary bits forming the test pattern are applied to the recognition logics. The pre-printed document also carries a set of patterns which, when scanned, produce a binary bit pattern identifying the test bit pattern. This identification is compared with the identification bit pattern produced by the recognition logics. An equal comparison indicates that the recognition logics are functioning properly. An error condition causes the pre-printed pattern to be displayed. The machine operator or maintenance man can read the display and determine which recognition logics should be probed to find the error.
Inventors
- 👤 J Linnerooth
- 👤 E Rosen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:40
CPC Classifications
G; G06; G06V; G06V10/00; G06V10/98; G06V10/987
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
220 words
In a pattern recognition machine including scanner means for scanning patterns on documents to generate a plurality of bits for recognizing the pattern scanned and recognition means for recognizing the patterns scanned, the improvement comprising: test bit pattern generation means for generating a test bit pattern of recognition data representative of a single pattern in response to said scanner means scanning a plurality of two distinguishing patterns by logically examining bit conditions of first predetermined bits of said plurality of bits generated by said scanner means in response to scanning one of said distinguishing patterns and generating a bit having a binary one value when the bit conditions of said first predetermined bits meet predetermined logical conditions and by logically examining second predetermined bits of said plurality of bits generated by said scanner means in response to scanning the other of said distinguishing patterns and generating a bit having a binary zero value when the bit conditions of said second predetermined bits meet predetermined logical conditions whereby the so generated binary one and zero bits form said test bit pattern; means for applying said test bit pattern to said recognition means; means for representing the identity of said test bit pattern; and means for comparing the identity of said test bit pattern with the identity produced by said recognition means.
Claim 2
Dependent Claim
220 words
In a pattern recognition machine including scanner means for scanning patterns on documents to generate a plurality of bits for recognizing the pattern scanned and recognition means for recognizing the patterns scanned, the improvement comprising: test bit pattern generation means for generating a test bit pattern of recognition data representative of a single pattern in response to said scanner means scanning a plurality of two distinguishing patterns by logically examining bit conditions of first predetermined bits of said plurality of bits generated by said scanner means in response to scanning one of said distinguishing patterns and generating a bit having a binary one value when the bit conditions of said first predetermined bits meet predetermined logical conditions and by logically examining second predetermined bits of said plurality of bits generated by said scanner means in response to scanning the other of said distinguishing patterns and generating a bit having a binary zero value when the bit conditions of said second predetermined bits meet predetermined logical conditions whereby the so generated binary one and zero bits form said test bit pattern; means for applying said test bit pattern to said recognition means; means for representing the identity of said test bit pattern; and means for comparing the identity of said test bit pattern with the identity produced by said recognition means.
Claim 3
Dependent Claim
44 words
The pattern recognition machine of claim 1 further comprising: means responsive to said comparing means for displaying the patterns scanned when said comparing means indicates that the identity of said test bit pattern does not compare with the identity produced by said recognition means.
Claim 4
Dependent Claim
25 words
The pattern recognition machine of claim 1 wherein said test bit pattern includes bits identifying which recognition logics are responsive to said test bit pattern.
Claim 5
Independent Claim
98 words
A method for generating test bit patterns for testing logics in a pattern recognition machine comprising the steps of: forming a sequence of two distinguishing patterns on a document; scanning said patterns to generate a plurality of bits for each pattern; and generating from said plurality of bits one type of signal in response to scanning one distinguishing pattern and another type of signal in response to scanning the other distinguishing pattern to form a test bit pattern from said one and another types of signals representing bits generated by said scanning means when scanning a single pattern.
Claim 6
Independent Claim
98 words
A method for generating test bit patterns for testing logics in a pattern recognition machine comprising the steps of: forming a sequence of two distinguishing patterns on a document; scanning said patterns to generate a plurality of bits for each pattern; and generating from said plurality of bits one type of signal in response to scanning one distinguishing pattern and another type of signal in response to scanning the other distinguishing pattern to form a test bit pattern from said one and another types of signals representing bits generated by said scanning means when scanning a single pattern.
Claim 7
Dependent Claim
39 words
The method for generating test bit patterNs of claim 4 further comprising the steps of: applying said test bit pattern to logic circuitry to be tested and checking the output signals from said logic circuitry for a predetermined response.
Claim 8
Dependent Claim
211 words
In a pattern recognition machine having scanner means for scanning patterns on documents to generate for each pattern scanned a plurality of data signals representative of the pattern scanned and logic circuitry having a plurality of branches selectively connectable to receive signals produced by said scanner means, the improvement comprising: test bit generating means responsive to said scanner means scanning a sequence of two distinguishing patterns to produce a test bit of one type from a plurality of bits generated by said scanner when one distinguishing pattern is scanned and a test bit of a second type from a plurality of bits generated by said scanner when the second distinguishing pattern is scanned; means for applying the test bit pattern produced by said test bit generating means to selected branches of said logic circuitry; means for selecting the branches of said logic circuitry to be tested; test bit pattern identification means having outputs for representing the output bits which should be produced by the selected branches of said logic circuitry if said selected branches are operating without error; and means responsive to said outputs from said test bit identification means and outputs from the selected branches for generating signals indicating that said selected branches are either operating with or without error.
Claim 9
Dependent Claim
211 words
In a pattern recognition machine having scanner means for scanning patterns on documents to generate for each pattern scanned a plurality of data signals representative of the pattern scanned and logic circuitry having a plurality of branches selectively connectable to receive signals produced by said scanner means, the improvement comprising: test bit generating means responsive to said scanner means scanning a sequence of two distinguishing patterns to produce a test bit of one type from a plurality of bits generated by said scanner when one distinguishing pattern is scanned and a test bit of a second type from a plurality of bits generated by said scanner when the second distinguishing pattern is scanned; means for applying the test bit pattern produced by said test bit generating means to selected branches of said logic circuitry; means for selecting the branches of said logic circuitry to be tested; test bit pattern identification means having outputs for representing the output bits which should be produced by the selected branches of said logic circuitry if said selected branches are operating without error; and means responsive to said outputs from said test bit identification means and outputs from the selected branches for generating signals indicating that said selected branches are either operating with or without error.
Claim 10
Dependent Claim
37 words
The pattern recognition machine of claim 6 wherein said means for selecting the branches of the logic circuitry to be tested selects gating bits for branch selection from test bits produced by said test bit generating means.
Claim 11
Dependent Claim
27 words
The pattern recognition machine of claim 6 wherein said test bit pattern identification means selects identification bits from test bits produced by said test bit generating means.
Claim 12
Dependent Claim
15 words
The pattern recognition machine of claim 6 wherein the two distinguishing patterns are printed characters.
Claim 13
Dependent Claim
15 words
The pattern recognition machine of claim 6 wherein the logic circuitry is pattern recognition circuitry.
References Cited (Backward Citations)
US3247508A
Cited
US3581074A
Cited
US3528006A
Cited
US3562710A
Cited
US3643069A
Cited
US3622877A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-23 | 1976-07-24 | 1977-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-23 | 1980-07-24 | 1981-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-23 | 1984-07-24 | 1985-01-23 | $7700.00 | Window Closed / Lapsed |