Waveform generator with accurate mark to space ratio

Claim 2

A waveform generator comprising: a. a frequency variable oscillator for generating a periodic signal voltage, b. a frequency divider for dividing the periodic signal by choosen integer, said frequency divider having an input terminal, responsive to the periodic signal voltage generated by the oscillator, and an output terminal, c. a switch means having a conducting and a non-conducting state and having a control element, for selecting one of said states, the frequency divider output terminal being connected to the control element for changing the state of conduction of the switch means in accordance with a change in a voltage level appearing at said output terminal, d. means for alternately changing the period of the periodic signal voltage from a first period to a second period as the state of said switch means is alternately changed from the conducting to the nonconducting state, whereby an output voltage having positive and negative transitions defining a waveform, with a mark-to-space ratio dependent on the ratio of the first to second periods of the periodic signal voltage is generated at the output terminal of the frequency divider said transitions occurring substantially in phase with the periodic signal voltage.

Claim 3

A waveform generator comprising: a. a capacitor controlled oscillator for generating a signal voltage with a rectangular waveform, the rectangular waveform having a first period dependent on a first capacitor, b. a binary counter having a counter input terminal and a counter output terminal, said input being responsive to the signal voltage generated by said oscillator, c. a transistor switch, the base of said switch being connected to said output terminal for changing the state of conduction of the transistor switch in accordance with a change in voltage level appearing at said output terminal, d. a second capacitor in series with the collectoremitter junction of the transistor switch for alternately changing the period of the rectangular waveform from the first period to a second period by alternately connecting the second capacitor in parallel with the first capacitor as the transistor switch is alternately switched into and out of conduction, whereby an output voltage having a rectangular waveform with a desired mark-to-space ratio is generated at the output terminal of the binary counter.

Claim 4

A waveform generator comprising: a. a capacitor controlled oscillator for generating a signal voltage with a rectangular waveform, the rectangular waveform having a first period dependent on a first capacitor, b. a binary counter having a counter input terminal and a counter output terminal, said input being responsive to the signal voltage generated by said oscillator, c. a transistor switch, the base of said switch being connected to said output terminal for changing the state of conduction of the transistor switch in accordance with a change in voltage level appearing at said output terminal, d. a second capacitor in series with the collectoremitter junction of the transistor switch for alternately changing the period of the rectangular waveform from the first period to a second period by alternately connecting the second capacitor in parallel with the first capacitor as the transistor switch is alternately switched into and out of conduction, whereby an output voltage having a rectangular waveform with a desired mark-to-space ratio is generated at the output terminal of the binary counter.

Claim 5

The invention as defined in claim 2 further comprising: an electronic gate for gating the signal voltage of said oscillator into the input terminal of the binary counter when said gate is enabled, whereby the output voltage Having a rectangular waveform with the desired mark-to-space ratio appears at the output terminal of the binary counter when said gate is enabled.

Claim 6

The invention as defined in claim 2 further comprising: a first electronic gate for gating the signal voltage of said oscillator into the input terminal of the binary counter when said gate is enabled, a second electronic gate, the second electronic gate having a first input gate terminal, a second input gate terminal and an output gate terminal, the output gate terminal of the second electronic gate being connected to enable the first electronic gate, the first input gate terminal being connected through an inverter to the output terminal of the binary counter and the second input gate terminal being arranged for connection to a control signal, whereby after the control signal is removed the output voltage at the binary counter output terminal maintains the logic states of the first and second electronic gates until the output voltage generated at the binary counter output terminal has completed a full cycle.

Claim 7

A waveform generator comprising: a. an operational amplifier, said amplifier having an amplifier first input terminal, an amplifier second input terminal and an amplifier output terminal, b. a first dual input NAND gate, one input of the first dual input NAND gate being connected to the amplifier output terminal, c. a binary counter, said counter having a counter input terminal, a counter first output terminal and a counter second output terminal, the counter first and second output terminals being conjugate counter output terminals, the counter input terminal being connected to the output of the first dual input NAND gate; d. a common terminal; e. a transistor switch, the base of the transistor switch being connected to the counter first output terminal, the emitter of the transistor switch being connected to the common terminal, f. a second dual input NAND gate, having a first input gate terminal and a second input gate terminal the output of the second dual input NAND gate being connected to the other input of the first dual input NAND gate, the first input of the second dual input NAND gate being connected to the counter second output terminal and the second input of the second dual input NAND gate being arranged for connection to a control potential; g. a first resistor connecting the amplifier first input terminal to the common terminal, a second resistor connecting the amplifier first input terminal to the amplifier output terminal, and a third resistor connecting the amplifier output terminal to the amplifier second input terminal; h. a first capacitor connecting the amplifier second input terminal to the common terminal; i. a second capacitor connecting the collector of the transistor switch to the amplifier second input terminal, whereby an output voltage having a rectangular waveform is generated at the output terminals of the binary counter when a control potential is applied to the second dual input NAND gate.

Claim 8

A waveform generator comprising: a. an operational amplifier, said amplifier having an amplifier first input terminal, an amplifier second input terminal and an amplifier output terminal, b. a first dual input NAND gate, one input of the first dual input NAND gate being connected to the amplifier output terminal, c. a binary counter, said counter having a counter input terminal, a counter first output terminal and a counter second output terminal, the counter first and second output terminals being conjugate counter output terminals, the counter input terminal being connected to the output of the first dual input NAND gate; d. a common terminal; e. a transistor switch, the base of the transistor switch being connected to the counter first output terminal, the emitter of the transistor switch being connected to the common terminal, f. a second dual input NAND gate, having a first input gate terminal and a second input gate terminal the output of the second dual input NAND gate being connected to the other input of the first dual input NAND gate, the first input of the second dual input NAND gate being connected to the counter second output terminal and the second input of the second dual input NAND gate being arranged for connection to a control potential; g. a first resistor connecting the amplifier first input terminal to the common terminal, a second resistor connecting the amplifier first input terminal to the amplifier output terminal, and a third resistor connecting the amplifier output terminal to the amplifier second input terminal; h. a first capacitor connecting the amplifier second input terminal to the common terminal; i. a second capacitor connecting the collector of the transistor switch to the amplifier second input terminal, whereby an output voltage having a rectangular waveform is generated at the output terminals of the binary counter when a control potential is applied to the second dual input NAND gate.