Circuit arrangement for connecting a plurality of frequency multiplier stages to a common fundamental frequency generator

Claim 2

A circuit arrangement for connecting a plurality of frequency multiplier stages, each producing a different output frequency, and only one of which operates at a specific time, to a common fundamental frequency generator, each of the frequency multiplier stages having an input and an ouTput, said circuit arrangement comprising a plurality of switching diodes each coupling the input of a corresponding one of the frequency multiplier stages to the fundamental frequency generator; a common output terminal; a plurality of bandpass filters each tuned to a different corresponding harmonic and each coupling the output of a corresponding one of the frequency multiplier stages to the common output terminal; and current supply means connected to the switching diodes for supplying current to the fundamental frequency generator via the switching diode of the operating frequency multiplier stage.

Claim 3

A circuit arrangement as claimed in claim 1, further comprising voltage cutoff means connected to each of the frequency multiplier states for cutting off all the frequency multiplier stages but the operating one simultaneously with the operation of said one of the frequency multiplier stages.

Claim 4

A circuit arrangement as claimed in claim 2, wherein each of the frequency multiplier stages has a step recovery semiconductor multiplier diode and bias means connected to the multiplier diode for shifting the bias of the multiplier diode of each of the frequency multiplier stages to be cut off from a normal operating bias to a high reverse bias.

Claim 5

A circuit arrangement as claimed in claim 2, wherein each of the frequency multiplier stages has a step recovering semiconductor multiplier diode and bias means connected to the multiplier diode for biasing the diode of each of the frequency multiplier stages to be cut off in the conductive direction.

Claim 6

A circuit arrangement as claimed in claim 3, further comprising cutoff voltage means having a plurality of resistors each connected to a corresponding one of the frequency multiplier stages for applying a cutoff voltage to the corresponding frequency multiplier stage and a plurality of short-circuit means each connected to a corresponding one of the resistors for short-circuiting the resistor of the frequency multiplier stage to be operated.

Claim 7

A circuit arrangement as claimed in claim 5, wherein each of the switching diodes is coupled in series between the common fundamental frequency generator and a corresponding one of the frequency multiplier stages so that the cutoff voltage applied to each of the frequency multiplier stages to be cut off by the cutoff voltage means simultaneously blocks the corresponding switching diode.

Claim 8

A circuit arrangement as claimed in claim 6, wherein the cutoff voltage means comprises a plurality of common resistors each connected to a corresponding one of the switching diodes for applying the cutoff voltage to the frequency multiplier stages, a plurality of RF chokes each connected between a corresponding one of the common resistors and a corresponding one of the switching diodes for applying the cutoff voltage to the switching diodes, and a plurality of load resistors each coupled between a corresponding one of the common resistors and the multiplier diode of a corresponding one of the frequency multiplier stages for codetermining the bias applied to each of the multiplier diodes, the voltage at a common point in the connection between the common resistor and the load resistor of a frequency multiplier stage to be operated being short-circuited.

Claim 9

A circuit arrangement as claimed in claim 6, wherein the cutoff voltage means comprises a plurality of common resistors each for applying the cutoff voltage to a corresponding one of the frequency multiplier stages, a plurality of RF chokes each connected to a corresponding one of the switching diodes for applying the cutoff voltage to the switching diodes, a plurality of transistor buffer stages each connected between a corresponding one of the RF chokes and a corresponding one of the common resistors, and a plurality of separate load resistors each coupled to the multiplier diode of a corresponding one of the frequency multiplier stages for codetermining the bias applied to each of the multiplier diodes and each connected in DC shunt wiTh a corresponding one of the transistor buffer stages, each of the transistor buffer stages having an emitter side connected to the corresponding common resistor and presenting a high resistance circuit relative to the load resistor when the corresponding frequency multiplier stage is cut off and supplying a conduction current of sufficient magnitude for the multiplier diode when the corresponding frequency multiplier stage is operated.

Claim 10

A circuit arrangement as claimed in claim 6, further comprising a plurality of harmonic traps each connected to a corresponding one of the switching diodes, each of the harmonic traps being for the harmonic to which the corresponding frequency multiplier stage is tuned.