Digital fundamental prp analyzer for pulse train signals

Claim 2

A pulse-repetition-period (PRP) analyzer comprising, in combination: means for converting an input waveform into a series of equal binary pulses, each occuring whenever said input waveform exceeds a predetermined level; means connected to said binary converter means for sorting the pulses therefrom into a successive series of pulse trains ordered according to their pulse repetition periods; means connected to said pulse-sorting means for rejecting the harmonics of any pulse train which is being passed through the PRP analyzer; means connected to said harmonic-rejection means for individually integrating said fundamental pulse trains, the integrating periods being weighted in proportion to the relative lengths of the periods of said pulse trains; and time-delay control means connected to said sorting means, said periodic-pulse rejection means and said weighted integrator means for synchronizing the operations of said means and for changing, according to a predetermined schedule, the time by which a signal passing through said sorting means is delayed.

Claim 3

A PRP analyzer as in claim 1, wherein said sorting means comprises a variable-length shift register and an AND gate known as the V-AND gate, said AND gate receiving as inputs both the input to and the output from said variable-length shift register.

Claim 4

A PRP analyzer as in claim 2, further including means for visually displaying the output of said weighted-integrator means.

Claim 5

A PRP analyzer as set forth in claim 2, wherein said time-delay control means comprises a function generator connected to a voltage-controlled oscillator.

Claim 6

A PRP analyzer as set forth in claim 2, wherein said periodic-pulse rejection means comprises a first shift register having parallel outputs, a plurality of AND gates, each connected to receive the output of a different one of said bits of said first register, a second shift register having parallel inputs, each connected to receive the output from a different one of said AND gates, the twO registers operating in opposite directions and each AND gate also receiving as an input the output of said V-AND gate, an inverter connected to receive as an input the output from the last bit of said second register, and an AND gate known as the P-AND gate receiving as inputs the inverter output and the output of said V-AND gate.

Claim 7

A pulse-repetition-period (PRP) analyzer comprising, in combination: means for converting an input waveform into a series of equal binary pulses, each occurring whenever said input waveform exceeds a predetermined amplitude level; means connected to said binary converter means for sorting the pulses therefrom into a successive series of pulse trains ordered according to their pulse repetition periods; means connected to said pulse-sorting means for rejecting the harmonics of any pulse train at the input the period of which is the same as the time delay provided by said sorting means; means connected to said harmonic-rejection means for individually integrating said fundamental pulse trains, the integrating periods being weighted in proportion to the relative lengths of the periods of said pulse trains; and time delay control means connected to said sorting means, said periodic-pulse rejection means and said weighted integrator means for synchronizing the operations of said means and for changing, according to a predetermined schedule, the time by which a signal passing through said sorting means is delayed.

Claim 8

A pulse-repetition-period (PRP) analyzer comprising, in combination: means for converting an input waveform into a series of equal binary pulses, each occurring whenever said input waveform exceeds a predetermined amplitude level; means connected to said binary converter means for sorting the pulses therefrom into a successive series of pulse trains ordered according to their pulse repetition periods; means connected to said pulse-sorting means for rejecting the harmonics of any pulse train at the input the period of which is the same as the time delay provided by said sorting means; means connected to said harmonic-rejection means for individually integrating said fundamental pulse trains, the integrating periods being weighted in proportion to the relative lengths of the periods of said pulse trains; and time delay control means connected to said sorting means, said periodic-pulse rejection means and said weighted integrator means for synchronizing the operations of said means and for changing, according to a predetermined schedule, the time by which a signal passing through said sorting means is delayed.

Claim 9

A PRP analyzer as in claim 6, wherein said sorting means comprises a variable-length shift register and an AND gate known as the V-AND gate, said V-AND gate receiving as inputs both the input to and the output from said variable-length shift register.

Claim 10

A PRP analyzer as in claim 7, further including means for visually displaying the output of said weighted-integrator means.

Claim 11

A PRP analyzer as in claim 7, wherein said time-delay control means comprises a function generator connected to a voltage-controlled oscillator.

Claim 12

A PRP analyzer as set forth in claim 7, wherein said periodic-pulse rejection means comprises a first shift register having parallel outputs, a plurality of AND gates, each connected to receive the output of a different one of said bits of said first register, a second shift register having parallel inputs, each connected to receive the output from a different one of said AND gates, the two registers operating in opposite directions and each AND gate also receiving as an input the output of said V-AND gate, an inverter connected to receive as an input the output from the last bit of said second register, and an AND gate known as the P-AND gate receiving as inputs the inverter output and the output of said V-AND gate.