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US3710349A Expired / Lapsed US ⏱️ 0.0 years remaining

Data transferring circuit arrangement for transferring data between memories of a computer system

Assignee: Fujitsu Ltd
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Filing: 1971-05-05
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Granted: 1973-01-09
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Expires: 1991-05-05
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Abstract

Abstract Data transferring means separate and independent from the central processing unit of a computer system and operating in parallel with the central processing unit transfers data between a first memory area and a second memory area in a memory. The data transferring means comprises a first register for storing the address of the data of the first memory area from which the data is successively transferred to the second memory area. A second register stores the address of the data of a second memory area to which the data is successively transferred from the second memory area. A third register stores addresses of the group of data transferred from the first memory area to the second memory area. Transfer means transfers data directly to the second position in the second memory area designated by the address information of the second register. First arithmetic means connected to the first register and the second register modifies the address information of the first register and the second register by the information of the transfer data. Second arithmetic means connected to the third register modifies the address information of the transfer data.

Inventors

  • 👤 O Miwa
  • 👤 Y Kayano

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 01:09
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/285

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 230 words
In a computer system for processing data stored therein, said computer system having at least one central processing unit, memory means including first and second memory areas, data transferring means separate and independent from the central processing unit and operating in parallel with the central processing unit for transferring data between the first memory area and the second memory area in the memory means, said data transferring means comprising a first register for storing the address of the first memory area from which said data is successively transferred to the second memory area, a second register for storing the address of the second memory area to which said data is successively transferred from the second memory area, a third register for storing addresses of data groups transferred from the first memory area to the second memory area, receiving means for receiving data directly from the position in the first memory area designated by the address information of the first register, transfer means for transferring data directly to the position in the second memory area designated by the address information of the second register, first arithmetic means connected to the first register and the second register for modifying the address information of the first register and the second register by the transferred data, and second arithmetic means connected to the third register for modifying the address information of the transferred data.
Claim 2
Dependent Claim 230 words
In a computer system for processing data stored therein, said computer system having at least one central processing unit, memory means including first and second memory areas, data transferring means separate and independent from the central processing unit and operating in parallel with the central processing unit for transferring data between the first memory area and the second memory area in the memory means, said data transferring means comprising a first register for storing the address of the first memory area from which said data is successively transferred to the second memory area, a second register for storing the address of the second memory area to which said data is successively transferred from the second memory area, a third register for storing addresses of data groups transferred from the first memory area to the second memory area, receiving means for receiving data directly from the position in the first memory area designated by the address information of the first register, transfer means for transferring data directly to the position in the second memory area designated by the address information of the second register, first arithmetic means connected to the first register and the second register for modifying the address information of the first register and the second register by the transferred data, and second arithmetic means connected to the third register for modifying the address information of the transferred data.

References Cited (Backward Citations)

US3411139A Cited
US3413613A Cited
US3525080A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-01-09 1976-07-10 1977-01-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-01-09 1980-07-10 1981-01-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-01-09 1984-07-10 1985-01-09 $7700.00 Window Closed / Lapsed

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