Detector for digitally transmitted multifrequency tones as utilized for signaling in a pulse code modulated telephone system

Claim 2

For use in a communication system including a switch center, apparatus for detecting the presence of information equivalent to multifrequency dialing signals, as transmitted sequentially over a transmission facility in pulse code modulated form to said switching center, said apparatus comprising: a plurality of registers serially connected to said transmission facility, sequentially operated in response to receipt of predetermined quantities of information in digital form to store a predetermined quantity of information in each of said registers in the received sequence, said plurality of registers including, a first register; a second register; a comparison circuit connected between said first and second register operated in response to determination that the relative digital value of information stored in said first register is greater than the value of information stored in said second register, first counting means; a first bistable circuit connected between said comparison circuit and said first counting means, set to a first state in response to operation of said comparison means; said first counting means operated in response to setting of said first bistable circuit to a first state.

Claim 3

Apparatus as claimed in claim 1 wherein; said comparison means are further operated in response to determination that the relative digital value of information stored in said first register is less than the value of information stored in said second register to set said first bistable circuit to a second state, a third register connected to said second register; first gating means connected between said comparison means and said first register and also connected between said comparison means and said third register and including logic circuit means for connecting said first bistable circuit to said first logic gating means, operated in response to said first bistable circuit operated to its second state to complete circuit connections from said third register to said comparison means, said comparison means further operated in response to determination that the relative digital value of information stored in said second register is greater than the value of information stored in said third register; second counting means; a second bistable circuit connected between said comparison means and said second counting means operated in response to said further operation of said comparison means to set said second bistable circuit to a first state, said second counting means operated in response to said second bistable circuit operation to a first state; second gating means connected to said first and to said second counting means operated in response to operation of said first and second counting means to decode the count stored therein and convert said decoded information into output signals representative of multifrequency dialing signals for use in said communication system.

Claim 4

Apparatus as claimed in claim 1 wherein said first register is of the serial input, parallel output type anD said second and third registers are of the parallel input, parallel output type.

Claim 5

Apparatus as claimed in claim 1 wherein any information stored in said second register is first transferred to said third register; and information stored in said first register is subsequently transferred to said second register, said information transfers effected in response to different enabling pulses originating in said switching center, said switching center further providing reset pulses periodically on a cyclic basis, whereby all of said registers are reset.

Claim 6

Apparatus as claimed in claim 4 wherein is further included: a third bistable circuit operated in response to operation of said first bistable circuit to its first state, to periodically provide a gating pulse in combination with one of said enabling pulses provided by said switching center, for operation of said second bistable means.

Claim 7

Apparatus as claimed in claim 4 wherein said reset pulses are further employed to reset said first and second counting means periodically.