Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
270 words
A system for detecting in a frame period the beginning of the transmit-time of both the message bursts and the address of each of a plurality of different stations in an asynchronous time division multiplex communication system via a communications satellite comprising: a source of bit stream including an address code and a message burst start signal code; first means coupled to said source to detect said address code in a given time slot of each of said frame periods; second means coupled to said first means to detect said start signal code in said given time slot of each of said frame periods and produce an identifying signal when said start signal is thusly detected; third means coupled to said second and first means to store said identifying signal of the preceding N frame periods and to store said address code of the corresponding preceding N frame periods, where N is an integer greater than two; fourth means coupled to said second means and said third means to determine by a first majority decision the actual presence of said start signal in said given time slot and to pass the next one of said start signal code for processing upon occurrence of a first positive majority decision; and fifth means coupled to said first means, said third means and said fourth means to determine, in response to said first positive majority decision, by a second majority decision the actual presence of said address code in said given time slot and to pass the next one of said address code for processing upon occurrence of a second positive majority decision.
Claim 2
Independent Claim
270 words
A system for detecting in a frame period the beginning of the transmit-time of both the message bursts and the address of each of a plurality of different stations in an asynchronous time division multiplex communication system via a communications satellite comprising: a source of bit stream including an address code and a message burst start signal code; first means coupled to said source to detect said address code in a given time slot of each of said frame periods; second means coupled to said first means to detect said start signal code in said given time slot of each of said frame periods and produce an identifying signal when said start signal is thusly detected; third means coupled to said second and first means to store said identifying signal of the preceding N frame periods and to store said address code of the corresponding preceding N frame periods, where N is an integer greater than two; fourth means coupled to said second means and said third means to determine by a first majority decision the actual presence of said start signal in said given time slot and to pass the next one of said start signal code for processing upon occurrence of a first positive majority decision; and fifth means coupled to said first means, said third means and said fourth means to determine, in response to said first positive majority decision, by a second majority decision the actual presence of said address code in said given time slot and to pass the next one of said address code for processing upon occurrence of a second positive majority decision.
Claim 3
Dependent Claim
50 words
A system according to claim 1, wherein said third means includes a first shift register having N section to store said identifying signal produced in N successive frame periods, and a second shift register having at least N sections to store said address code detected in N successive frame periods.
Claim 4
Dependent Claim
52 words
A system according to claim 1, wherein said third means includes a shift register having N sections coupled in common to said second means and said first means to store said identifying signal produced in N successive frame periods and to store said address code detected in said N successive frame periods.
Claim 5
Dependent Claim
76 words
A system according to claim 1, wherein said fourth means includes a first majority decision circuit coupled to said third means, a gate pulse generator coupled to said first majority decision circuit, and a first AND-circuit coupled to said second means and said gate pulse generator enabled by an output signal of said gate pulse generator to pass the next one of said start signal code for processing upon occurrence of said first positive majority decision.
Claim 6
Dependent Claim
23 words
A system according to claim 4, wherein said fifth means includes a second majority decision circuit coupled to said first majority decision circuit.
Claim 7
Dependent Claim
86 words
A system according to claim 4, wherein said third means includes a first shift register having N sections to store said identifying signal produced in N successive frame periods, a second shift register having N sections to store said address code detected in N successive frame periods, and a second AND-circuit coupled to said second means and said first AND-circuit, said second AND-circuit being enabled by said next one of said start signal code to shift the address code coincident therewith into said second shift register.
Claim 8
Dependent Claim
50 words
A system according to claim 5, wherein said third means further includes a timing source, a control means coupled to said second shift register, said timing source and said first AND-circuit to control the shifting of address codes between adjacent ones of said N sections of said second shift register.
Claim 9
Dependent Claim
22 words
A system according to claim 5, wherein said fifth means includes a second majority decision circuit coupled to said second shift register.
Claim 10
Dependent Claim
137 words
A system according to claim 1, wherein said third means includes a shift register having N sections coupled in common to said second means and said first means to store said identifying signal produced in N successive frame periods and to store said address code detected in said N successive frame periods; said fourth means includes a first majority decision circuit coupled to said shift register, a gate pulse generator coupled to said first majority decision circuit, and an AND-circuit coupled to said second means and said gate pulse generator enabled by an output signal of said gate pulse generator to pass the next one of said staRt signal code for processing upon occurrence of said first positive majority decision; and said fifth means includes a second majority decision circuit coupled to said first majority decision circuit.