Time slot memory circuit

Claim 2

In a time division system, a time slot memory circuit responsive to an input pulse in a time slot for thereafter providing output pulses in that time slot comprising an oscillator operating at a multiple of the system sampling frequency and started in response to an input pulse, and means for combining a positive zero crossing of the oscillator output with the output of a clock providing pulses defining system time slots to generate an output pulse in the time slot during which the input pulse occurred, said output pulse Being fed back as an input to the memory circuit.

Claim 3

The time slot memory circuit of claim 1 wherein said combining means includes voltage level shifting means connected to said oscillator.

Claim 4

The time slot memory circuit of claim 2 wherein said combining means further includes circuitry arranged to disable said combining means except during the last half cycle of oscillation of said oscillator prior to the occurrence of said input pulse time slot.

Claim 5

In a time division system, a time slot memory circuit activated by an input pulse in a time slot for thereafter providing output pulses at the system frame rate in the time slot during which the input pulse occurs comprising a gate having a first input, a second input and a third input, and an output over which said output pulses are provided, said first input being connected to a clock which supplies pulses defining time slots, an oscillator operating a N times the system sampling frequency, means connecting said oscillator to said second gate input, a monostable multivibrator having an input and an output, said multivibrator output being connected to said third gate input, said multivibrator being arranged to provide a pulse at said multivibrator output which disables said gate for (2N-1)/2 cycles of said oscillator after a pulse at said multivibrator input, clamping means having an input, said clamping means being connected to said oscillator and responsive to a signal on said clamping means input for clamping said oscillator for the duration of said signal, and means for applying said input pulse and said output pulses to said clamping means input and said multivibrator input.

Claim 6

In a time division system, a time slot memory circuit activated by an input pulse in a time slot for thereafter providing output pulses at the system frame rate in the time slot during which the input pulse occurs comprising a gate having a first input, a second input and a third input, and an output over which said output pulses are provided, said first input being connected to a clock which supplies pulses defining time slots, an oscillator operating a N times the system sampling frequency, means connecting said oscillator to said second gate input, a monostable multivibrator having an input and an output, said multivibrator output being connected to said third gate input, said multivibrator being arranged to provide a pulse at said multivibrator output which disables said gate for (2N-1)/2 cycles of said oscillator after a pulse at said multivibrator input, clamping means having an input, said clamping means being connected to said oscillator and responsive to a signal on said clamping means input for clamping said oscillator for the duration of said signal, and means for applying said input pulse and said output pulses to said clamping means input and said multivibrator input.

Claim 7

A time slot memory circuit in accordance with claim 4 wherein said oscillator includes an L-C tank circuit and said clamping means is arranged to cause a constant current to flow through said tank circuit in response to a signal on said clamping means input.

Claim 8

A time slot memory circuit in accordance with claim 4 wherein said connecting means includes a level shifter connected between said oscillator and said second gate input, said level shifter being arranged so as to enable said second gate input when the output voltage of said oscillator is at a predetermined negative voltage.

Claim 9

A time slot memory circuit for providing pulses in a predetermined time slot in successive system cycles in a time division switching system having a predetermined sampling frequency and a system clock defining system time slots, the memory circuit comprising an oscillator operating at a multiple of the system sampling frequency and having an input and an output, combining means having an output and a plurality of inputs to one of which is connected the system clock, voltage level shifting means connecting said oscillator output to another of said combining means inputs, disabling means connected to a third of said combining means inputs for disabling said combining means except during the last half cycle of oscillation of said oscillator prior to the occurrence of the predetermined time slot, an oscillator clamp circuit connected to said oscillator input, and means connecting said combining means output to said oscillator clamp circuit.

Claim 10

A time slot memory circuit for providing pulses in a predetermined time slot in successive system cycles in a time division switching system having a predetermined sampling frequency and a system clock defining system time slots, the memory circuit comprising an oscillator operating at a multiple of the system sampling frequency and having an input and an output, combining means having an output and a plurality of inputs to one of which is connected the system clock, voltage level shifting means connecting said oscillator output to another of said combining means inputs, disabling means connected to a third of said combining means inputs for disabling said combining means except during the last half cycle of oscillation of said oscillator prior to the occurrence of the predetermined time slot, an oscillator clamp circuit connected to said oscillator input, and means connecting said combining means output to said oscillator clamp circuit.