US3708788A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Associative memory cell driver and sense amplifier circuit
Assignee: International Business Machines Corp
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Filing: 1971-11-11
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Granted: 1973-01-02
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Expires: 1991-11-11
Abstract
Abstract An improved driver permits the driving of a functional array of four-state cells having only two bit lines per cell while providing for the writing of any one of four possible logical states (0, 1, X, Y) into the array during one write cycle. In a preferred form, the improved driver includes a first pair of field effect transistors which are selectively operated during write and search/select cycles to couple a pair of junctions (or nodes) in the driver to the pair of data bit lines of a cell. In the absence of ''''don''t care'''' signals, additional field effect transistors respond to input data to the driver to apply complementary signals (01 or 10) to the nodes for application to the respective bit lines. In response to the receipt of ''''don''t care'''' signals, field effect transistors in the driver electrically connect the two nodes causing the same selected signal level (00 or 11) to be applied to the data bit lines. A pair of field effect transistors are selectively operated during read cycles to couple the data bit lines to respective sense amplifiers. In a preferred form, the driver is comprised of complementary field effect transistors operated in the enhancement mode.
Inventors
- 👤 J Dailey
- 👤 J Surgent
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:50
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
163 words
A driver circuit for an associative array having four-state cells and only a pair of data lines for one cycle writing of data into, one cycle search/select, and one cycle reading of data from each cell, said circuit comprising a first input line for receiving binary data signals, a second input line for receiving don''t care signals, a pair of junctions, field effect transistor means connected to the first and second lines and responsive to the logical value of the data signal concurrent with the presence of a don''t care signal for applying the same selected data signal value to both junctions, field effect transistor means connected to the first and second lines and responsive to the logical value of the data signal concurrent with the absence of a don''t care signal for applying complementary data signal values selectively to the junctions, and field effect transistor means selectively operated during search/select and write cycles for coupling each junction to a respective data line.
Claim 2
Dependent Claim
163 words
A driver circuit for an associative array having four-state cells and only a pair of data lines for one cycle writing of data into, one cycle search/select, and one cycle reading of data from each cell, said circuit comprising a first input line for receiving binary data signals, a second input line for receiving don''t care signals, a pair of junctions, field effect transistor means connected to the first and second lines and responsive to the logical value of the data signal concurrent with the presence of a don''t care signal for applying the same selected data signal value to both junctions, field effect transistor means connected to the first and second lines and responsive to the logical value of the data signal concurrent with the absence of a don''t care signal for applying complementary data signal values selectively to the junctions, and field effect transistor means selectively operated during search/select and write cycles for coupling each junction to a respective data line.
Claim 3
Dependent Claim
45 words
The circuit set forth in claim 1 further comprising a third line for receiving read signals, sense amplifiers means, and field effect transistor means connected to the third line and responsive to each read signal for coupling the data lines to the sense amplifier means.
Claim 4
Dependent Claim
149 words
The circuit set forth in claim 1 wherein the first-mentioned field effect transistor means comprises first and second complementary field effect transistors of the insulated gate type connected in series and having their gate electrodes connected to each other and to the first input line and having the connection therebetween coupled to one of said junctions for applying data signals to said one junction, third and fourth complementary field effect transistors of the insulated gate type connected in series and having their gate electrodes connected to each other and to the second input line, and a fifth field effect transistor of the insulated gate type having its source and drain terminals connected to respective ones of the junctions and having its gate electrode connected to the connection between the third and fourth transisters for short-circuiting the junctions in the presence of don''t care signals on the second input line.
Claim 5
Dependent Claim
92 words
The circuit set forth in claim 3 wherein the second-mentioned field effect transistor means comprises said first and second transistors, and a sixth field effect transistor of the insulated gate type having its gate electrode coupled to said second input line and having its source and drain terminals connected to the first input line and to the junction other then said one juNction for coupling data signals to the other junction complementary to the data signals at the one junction in the absence of don''t care signals on the second input line.
Claim 6
Dependent Claim
64 words
The circuit set forth in claim 4 wherein the third-mentioned field effect transistor means comprises a pair of field effect transistors each having source and drain terminals connected between a respective one of the junctions and a respective one of the data lines and having gate electrodes for receiving signals for turning on the latter transistors to couple the junctions to the data lines.
Claim 7
Dependent Claim
159 words
A driver circuit for an associative array having four-state cells and only a pair of data lines for one cycle writing of data into and one cycle reading of data from each cell and one cycle search/select, said circuit comprising a first input line for receiving binary data signals, a second input line for receiving don''t care signals, a pair of junctions, switching means connected to the first and second lines and responsive to the logical value of the data signal concurrent with the presence of a don''t care signal for applying the same selected data signal valve to the both junctions, switching means connected to the first and second lines and responsive to the logical value of the data signal concurrent with the absence of a don''t care signal for applying complementary data signal values selectively to the junctions, and switching means selectively operated during search/select and write cycles for coupling each junction to a respective data line.
Claim 8
Dependent Claim
159 words
A driver circuit for an associative array having four-state cells and only a pair of data lines for one cycle writing of data into and one cycle reading of data from each cell and one cycle search/select, said circuit comprising a first input line for receiving binary data signals, a second input line for receiving don''t care signals, a pair of junctions, switching means connected to the first and second lines and responsive to the logical value of the data signal concurrent with the presence of a don''t care signal for applying the same selected data signal valve to the both junctions, switching means connected to the first and second lines and responsive to the logical value of the data signal concurrent with the absence of a don''t care signal for applying complementary data signal values selectively to the junctions, and switching means selectively operated during search/select and write cycles for coupling each junction to a respective data line.
Claim 9
Dependent Claim
44 words
The circuit set forth in claim 6 further comprising a third line for receiving read signals, sense amplifier means, field effect transistor means connected to the third line and responsive to each read signal for coupling the data lines to the sense amplifier means.
Claim 10
Dependent Claim
25 words
The circuit set forth in claim 6 wherein the switching means are comprised solely of insulated gate field effect transistors of the same conductivity type.
Claim 11
Dependent Claim
169 words
A driver circuit for an associative array having four-state cells and only a pair of data lines for writing of data into and searching data in each cell, said circuit comprising a first input line for receiving binary data signals, a second input line for receiving don''t care signals, a pair of junctions, switching means comprised of insulated gate field effect transistors connected to the first and second lines and responsive to the logical value of the data signal concurrent with the presence of a don''t care signal for applying the same selected data signal value concurrently to both junctions, switching means comprised of insulated gate field effect transistors connected to the first and second lines and responsive to the logical value of the data signal concurrent with the absence of a don''t care signal for concurrently applying complementary data signal values selectively to the junctions, and switching means selectively operated during search/select and write cycles for concurrently coupling each junction to a respective one of the data lines.
Claim 12
Dependent Claim
169 words
A driver circuit for an associative array having four-state cells and only a pair of data lines for writing of data into and searching data in each cell, said circuit comprising a first input line for receiving binary data signals, a second input line for receiving don''t care signals, a pair of junctions, switching means comprised of insulated gate field effect transistors connected to the first and second lines and responsive to the logical value of the data signal concurrent with the presence of a don''t care signal for applying the same selected data signal value concurrently to both junctions, switching means comprised of insulated gate field effect transistors connected to the first and second lines and responsive to the logical value of the data signal concurrent with the absence of a don''t care signal for concurrently applying complementary data signal values selectively to the junctions, and switching means selectively operated during search/select and write cycles for concurrently coupling each junction to a respective one of the data lines.
Claim 13
Dependent Claim
21 words
The circuit of claim 9 wherein the switching means comprise complementary insulated gate field effect transistors operated in the enhancement mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-02 | 1976-07-03 | 1977-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-02 | 1980-07-03 | 1981-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-02 | 1984-07-03 | 1985-01-02 | $7700.00 | Window Closed / Lapsed |