US3708757A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Oscillator loop including two double valued mosfet delay networks
Assignee: Arris Technology Inc
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Filing: 1971-07-07
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Granted: 1973-01-02
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Expires: 1991-07-07
Abstract
Abstract An MOS oscillator is disclosed in which a pair of delay networks are provided, each having two inputs and two outputs, each network having the operating characteristic that a change in one of its inputs in a given sense produces a change in its outputs in a relatively short time and a change in the other of its inputs in that given sense produces a change in its outputs in a relatively long time, the two networks having their inputs and outputs cross-connected. The networks may be formed of MOS devices, all of them on a single substrate. From such a network two sets of outputs are obtained, one set being in the form of complementary pulses and the other set being in the form of complementary square waves. The frequency of operation of the oscillator can be controlled by varying the voltage applied to MOS devices in the circuit which function as resistors, thereby modifying the time constant of capacitor-charging circuits in which those resistors are present.
Inventors
- 👤 B Deluccia
- 👤 G Russo
- 👤 G Savarese
- 👤 G Campellone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:45
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/354
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
116 words
An oscillator comprising first and second networks having inputs A, B, and A'' and B'' respectively, and outputs X, Y, and X'' and Y'' respectively, and each having the operating characteristic that a change in input A or A'' in a given sense produces a change in outputs X and Y or X'' and Y'' respectively in a given sense in a time D and a change in inputs B or B'' in said given sense produces a change in outputs X and Y or X'' and y'' respectively in a time d, where D is greater than d, and electrical connections between X and B'', Y and A'', X'' and A, and Y'' and B.
Claim 2
Dependent Claim
116 words
An oscillator comprising first and second networks having inputs A, B, and A'' and B'' respectively, and outputs X, Y, and X'' and Y'' respectively, and each having the operating characteristic that a change in input A or A'' in a given sense produces a change in outputs X and Y or X'' and Y'' respectively in a given sense in a time D and a change in inputs B or B'' in said given sense produces a change in outputs X and Y or X'' and y'' respectively in a time d, where D is greater than d, and electrical connections between X and B'', Y and A'', X'' and A, and Y'' and B.
Claim 3
Dependent Claim
16 words
The oscillator of claim 1, in which said inputs are complementary and said outputs are complementary.
Claim 4
Dependent Claim
37 words
The oscillator of claim 1, in which each of said networks comprises a delay network having said operative characteristic followed by one or more inverter stages, whereby the outputs X, Y and X'' and Y'' are sharpened.
Claim 5
Dependent Claim
16 words
The oscillator of claim 3, in which said inputs are complementary and said outputs are complementary.
Claim 6
Dependent Claim
100 words
The oscillator of claim 1, in which each of said networks comprises a series circuit comprising a first voltage source, a first transistor having a control electrode, a resistor, a second transistor having a control electrode and a second voltage source, the inputs of said network being connected to said control electrodes respectively, a capacitor connected between the said second voltage source and a point between said first transistor and said resistor, and means for producing first and second signals corresponding to the potential of said point and to the complement thereof, said first and second signals comprising said outputs.
Claim 7
Dependent Claim
17 words
The oscillator of claim 5, in which said signal producing means comprises one or more inverter stages.
Claim 8
Dependent Claim
11 words
The oscillator of claim 5, in which said transistors are FETs.
Claim 9
Dependent Claim
41 words
The oscillator of claim 7, in which said resistor comprises a transistor having a control electrode, and variable biasing means operatively connected to said control electrode, thereby to vary the magnitude of resistance thereof and hence the frequency of said oscillator.
Claim 10
Dependent Claim
12 words
The oscillator of claim 8, in which said resistor-transistor comprises a FET.
Claim 11
Dependent Claim
41 words
The oscillator of claim 5, in which said resistor comprises a transistor having a control electrode, and variable biasing means operatively connected to said control electrode, thereby to vary the magnitude of resistance thereof and hence the frequency of said oscillator.
Claim 12
Dependent Claim
12 words
The oscillator of claim 10, in which said resistor-transistor comprises a FET.
Claim 13
Dependent Claim
11 words
The oscillator of claim 6, in which said transistors are FETs.
Claim 14
Dependent Claim
41 words
The oscillator of claim 12, in which said resistor comprises a transistor having a control electrode, and variable biasing means operatively connected to said control electrode, thereby to vary the magnitude of resistance thereof and hence the frequency of said oscillator.
Claim 15
Dependent Claim
12 words
The oscillator of claim 13, in which said resistor-transistor comprises a FET.
Claim 16
Dependent Claim
50 words
The oscillator of claim 9, in which said biasing means comprises a FET in series with a resistor and connected across a voltage source to define a voltage divider, said control electrode of said resistor-transistor being connected to a point between said biasing means FET and said biasing means resistor.
Claim 17
Dependent Claim
36 words
In combination with the oscillator of claim 15, a terminal electrically connected to said point between said biasing means FET and said biasing means resistor and adapted to be connected to an external variable voltage source.
Claim 18
Dependent Claim
23 words
The oscillator of claim 7, in which all of said FETs of said first and second networks are formed on a single Substrate.
Claim 19
Dependent Claim
23 words
The oscillator of claim 9, in which all of said FETs of said first and second networks are formed on a single substrate.
Claim 20
Dependent Claim
23 words
The oscillator of claim 11, in which all of said FETs of said first and second networks are formed on a single substrate.
References Cited (Backward Citations)
US3562559A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-02 | 1976-07-03 | 1977-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-02 | 1980-07-03 | 1981-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-02 | 1984-07-03 | 1985-01-02 | $7700.00 | Window Closed / Lapsed |