US3708657A
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US
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Numerical conversion apparatus for interferometer position transducer
Assignee: General Electric Co
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Filing: 1968-02-29
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Granted: 1973-01-02
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Expires: 1988-02-29
Abstract
Abstract A digitally operable, numerically controlled machine is described which employs an interferometer for position feedback together with a fringe count conversion apparatus capable of operating in a scale of 1, scale of 10, or scale of 100 to accommodate a wide range of machining speeds. The fringe count conversion apparatus converts an input series of electric signal pulses indicative of a quantity being measured (such as distance) into a digital count of standard measurement units. The apparatus is comprised by a digital integrator having an integrand register, a minor sum remainder register and a major sum remainder register with all of the registers being substantially equal in length. A known conversion factor is stored in digital form in the integrand register, and arithmetic processing means are provided for selectively entering values equal to the conversion factor stored in the integrand register into one of the remainder registers in response to the input series of electric signal pulses. The arithmetic processing means also serves to transfer overflow values from the minor sum remainder register into the major sum remainder register whereby the value accumulated in the major and minor sum remainder registers is indicative of the quantity being measured in standard measurement units such as inches or centimeters. The conversion apparatus operates with binary coded decimal digit values and the binary digits of corresponding decimal digit significance are time sequentially grouped in interlaced serially adjoining time relationship whereby processing operations of the arithmetic processing means on binary coded digits of corresponding decimal digit significance is facilitated.
Inventors
- 👤 L Kelling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:53
CPC Classifications
H; H03; H03K; H03K21/00; G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H03K21/02
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
334 words
A digitally operable conversion apparatus for converting an input series of electric signal pulses indicative of a quantity being measured in a known but nonstandard measurement unit, the input signal pulses including a positive or negative direction indication, into a digital count of standard measurement units likewise indicative of the quantity being measured, said apparatus comprising: A. a digital integrator having an integrand register, a minor sum remainder register and a major sum remainder register, all of the registers being substantially equal in length and the known conversion being stored as digital values in the integrand register, B. and arithmetic processing means for selectively accumulating digital values equal to the conversion factor stored in the integrand register into one of the remainder registers in response to the input series of electric signal pulses and for transferring overflow values from the minor sum remainder register into the major sum remainder register whereby the value accumulated in the major and minor sum remainder registers is indicative of the quantity being measured in standard measurement units, said arithmetic processing means including; 1. logic cIrcuit means for selectively adding or subtracting values of the conversion factor stored in the integrand register into at least one of the remainder registers in response to the direction indication of the input electric signal pulses, 2. enabling circuit means responsive to the direction indication of the input signal pulses coupled to and controlling the operation of the logic circuit means whereby the logic circuit means selectively is caused to operate in either the additive or subtractive mode, 3. a circulatable register comprising a delay line recirculating means having its output connected to the input of said logic circuit means and its input connected to the output of said logic circuit means, and 4. timing circuit means for circulating said digital values to be processed through the closed loop comprised by said logic circuit means and said circulatable register in stepped time sequential relationship with the processing operations of the logic circuit means.
Claim 2
Dependent Claim
334 words
A digitally operable conversion apparatus for converting an input series of electric signal pulses indicative of a quantity being measured in a known but nonstandard measurement unit, the input signal pulses including a positive or negative direction indication, into a digital count of standard measurement units likewise indicative of the quantity being measured, said apparatus comprising: A. a digital integrator having an integrand register, a minor sum remainder register and a major sum remainder register, all of the registers being substantially equal in length and the known conversion being stored as digital values in the integrand register, B. and arithmetic processing means for selectively accumulating digital values equal to the conversion factor stored in the integrand register into one of the remainder registers in response to the input series of electric signal pulses and for transferring overflow values from the minor sum remainder register into the major sum remainder register whereby the value accumulated in the major and minor sum remainder registers is indicative of the quantity being measured in standard measurement units, said arithmetic processing means including; 1. logic cIrcuit means for selectively adding or subtracting values of the conversion factor stored in the integrand register into at least one of the remainder registers in response to the direction indication of the input electric signal pulses, 2. enabling circuit means responsive to the direction indication of the input signal pulses coupled to and controlling the operation of the logic circuit means whereby the logic circuit means selectively is caused to operate in either the additive or subtractive mode, 3. a circulatable register comprising a delay line recirculating means having its output connected to the input of said logic circuit means and its input connected to the output of said logic circuit means, and 4. timing circuit means for circulating said digital values to be processed through the closed loop comprised by said logic circuit means and said circulatable register in stepped time sequential relationship with the processing operations of the logic circuit means.
Claim 3
Dependent Claim
41 words
enabling circuit means responsive to the direction indication of the input signal pulses coupled to and controlling the operation of the logic circuit means whereby the logic circuit means selectively is caused to operate in either the additive or subtractive mode,
Claim 4
Dependent Claim
41 words
enabling circuit means responsive to the direction indication of the input signal pulses coupled to and controlling the operation of the logic circuit means whereby the logic circuit means selectively is caused to operate in either the additive or subtractive mode,
Claim 5
Dependent Claim
58 words
A digitally operable conversion apparatus according to claim 1 wherein the apparatus operates with binary coded decimal digits and the binary digits of corresponding decimal digit significance are time sequentially grouped together and the groupings interlaced in serial sequence whereby processing operations of the arithmetic processing means on binary coded digits of corresponding decimal digit significance is facilitated.
Claim 6
Dependent Claim
97 words
A digitally operable conversion apparatus according to claim 2 wherein the digital arithmetic processing means processes a single binary coded decimal digital value in a single processing cycle and imposes a time delay equal to a single binary coded decimal digital value during the processing cycle whereby a binary coded decimal digital value appearing at the output of the arithmetic processing means selectively may be fed back in timed sequence to an input of the arithmetic processing means as one of the inputs thereof for addition or subtraction to the next succeeding binary coded decimal digital value.
Claim 7
Dependent Claim
34 words
a circulatable register comprising a delay line recirculating means having its output connected to the input of said logic circuit means and its input connected to the output of said logic circuit means, and
Claim 8
Dependent Claim
34 words
a circulatable register comprising a delay line recirculating means having its output connected to the input of said logic circuit means and its input connected to the output of said logic circuit means, and
Claim 9
Dependent Claim
39 words
timing circuit means for circulating said digital values to be processed through the closed loop comprised by said logic circuit means and said circulatable register in stepped time sequential relationship with the processing operations of the logic circuit means.
Claim 10
Dependent Claim
39 words
timing circuit means for circulating said digital values to be processed through the closed loop comprised by said logic circuit means and said circulatable register in stepped time sequential relationship with the processing operations of the logic circuit means.
Claim 11
Dependent Claim
188 words
A digitally operable conversion apparatus according to claim 3 wherein the apparatus is capable of processing three different time sequential functions with each function corresponding to the processing operations performed with relation to one axis of a three orthogonal axes system and wherein each function is comprised of three words with each word forming the conversion factor integrand register, minor sum remainder register, and major sum remainder register, respectively, for a given function, the functions and words being arrayed on the delay line recirculating means in sequential time interlaced relationship in a manner such that the second word of a given function is occupied by the conversion factor integrand register of that function, the third word of the given function is occupied by the minor sum remainder register of that function, and the first word of the next succeeding function is occupied by the major sum remainder register of the preceding function whereby all three functions are arrayed and continuously recirculated through the delay line recirculating means and interconnected logic circuit means in sequential time interlaced relationship by the timing circuit means, and improved processed speeds are obtained.
Claim 12
Dependent Claim
69 words
A digitally operable conversion apparatus according to claim 4 wherein there are three sets of input electric signal pulses, one for each of the orthogonal axes and wherein each set of signal pulses comprises the output signal pulses of an interferometer position measuring device for a respective axis, and means are provided for selectively changing the conversion factor stored in the integrand register for each of the three functions.
Claim 13
Dependent Claim
71 words
A digitally operable conversion apparatus according to claim 5 wherein the means for changing the conversion factor includes sensing means for sensing the environmental conditions affecting the accuracy of the interferometer measuring device, and automatic means responsive to the output of said sensing means for automatically changing the conversion factor in response to changes in the environmental conditions in a manner so as to optimize the accuracy of the distance measurement.
Claim 14
Dependent Claim
145 words
A digitally operable conversion apparatus according to claim 3 further comprising readout circuit means for selectively reading out the value stored in the major sum remainder register, said readout circuit means including complementing circuit means for reading out complemented numbers stored in the major sum remainder register, the complementing circuit means comprising complemented number sensing circuit means for sensing the existence of a complemented number stored in the major sum remainder register, complement enabling circuit means operatively coupled to said complement number sensing circuit means and to said arithmetic processing means for enabling the arithmetic processing means to subtract the complemented number from zero and to provide a true negative number at its output, and sign indicating circuit means responsive to the complemented number sensing circuit means for providing an output sign signal indicative of the negative character of a complemented number being read out.
Claim 15
Dependent Claim
136 words
A digitally operable conversion apparatus according to claim 7 wherein the complementing circuit means further includes bypass shift register means operatively coupled intermediate the input and output of the delay line recirculating means, bypass enabling circuit means responsive to said complemented number sensing circuit means for enabling said bypass shift register means to bypass a complemented number being read out around the arithmetic processing means and back into the input to the delay line recirculating means during a complementing readout operation, and bypass inhibiting circuit means responsive to the complemented number sensing circuit means and coupled intermediate the output of the arithmetic processing means and the input to the delay line recirculating means for preventing the true form of the complemented number from being read into the delay line recirculation means during a complementing readout operation.
Claim 16
Dependent Claim
187 words
A digitally operable conversion apparatus according to claim 8 wherein the apparatus is capable of processing three different time sequential functions with each function corresponding to the processing operations performed with relation to one axis of a three orthogonal axes system and wherein each function is comprised of three words with each word forming the conversion factor integrand register, minor sum remainder register, and major sum remainder register, respectively, for a given function, the functions and words being arrayed on the delay line recirculating means in sequential interlaced relationship in a manner such that the second word of a given function is occupied by the conversion factor integrand register of that function, the third word of the given function is occupied by the minor sum remainder register of that function, and the first word of the next succeeding function is occupied by the major sum remainder register of the preceding function whereby all three functions are arrayed and continuously recirculated through the delay line recirculating means and interconnected logic circuit means in sequential time interlaced relationship by the timing circuit means, and improved processing speeds are obtained.
Claim 17
Dependent Claim
232 words
In a numerical control, digitally operable conversion apparatus for converting an input series of electric signal pulses indicative of a quantity being measured in a known but nonstandard measurement unit into a digital count of standard measurement units likewise indicative of the quantity being measured, said apparatus comprising a digital integrator having an integrand register, a minor sum remainder register and a major sum remainder register, all of the registers being substantially equal in length and the known conversion factor being stored in digital form in the integrand register, arithmetic processing means for selectively summing values equal to the conversion factor stored in the integrand register into one of the remainder registers in response to the input series of electric signal pulses and for transferring overflow values from the minor sum remainder register into the major sum remainder register whereby the value accumulated in the major and minor sum remainder registers is indicative of the quantity being measured in standard measurement units, and scaling means for selective entering the conversion factor into the remainder registers either on a one for one basis wherein one conversion factor is entered for each input signal pulse or known multiples of the conversion factor are entered in a single cycle of operation of the arithmetic processing means for an equal multiple number of input signal pulses whereby improved processing speeds of the conversion apparatus are obtained.
Claim 18
Dependent Claim
232 words
In a numerical control, digitally operable conversion apparatus for converting an input series of electric signal pulses indicative of a quantity being measured in a known but nonstandard measurement unit into a digital count of standard measurement units likewise indicative of the quantity being measured, said apparatus comprising a digital integrator having an integrand register, a minor sum remainder register and a major sum remainder register, all of the registers being substantially equal in length and the known conversion factor being stored in digital form in the integrand register, arithmetic processing means for selectively summing values equal to the conversion factor stored in the integrand register into one of the remainder registers in response to the input series of electric signal pulses and for transferring overflow values from the minor sum remainder register into the major sum remainder register whereby the value accumulated in the major and minor sum remainder registers is indicative of the quantity being measured in standard measurement units, and scaling means for selective entering the conversion factor into the remainder registers either on a one for one basis wherein one conversion factor is entered for each input signal pulse or known multiples of the conversion factor are entered in a single cycle of operation of the arithmetic processing means for an equal multiple number of input signal pulses whereby improved processing speeds of the conversion apparatus are obtained.
Claim 19
Dependent Claim
107 words
A digitally operable conversion apparatus according to claim 10 wherein the input signal pulses include a positive or negative direction indication and wherein the arithmetic processing means includes logic circuit means for selectively adding or subtracting the conversion factor values stored in the integrand register into at least one of the remainder registers in response to the direction indicative of the input electric signal pulses, and enabling circuit means responsive to the direction indication of the input signal pulses coupled to and controlling the operation of the logic circuit means whereby the logic circuit means selectively is caused by operate in either the additive or subtractive mode.
Claim 20
Dependent Claim
90 words
A digitally operable conversion apparatus according to claim 11 wherein the arithmetic processing means is comprised by logic circuit means, delay line recirculating means having its output coupled to the input of the logic circuit means and its input coupled to the output of the logic circuit means, and timing circuit means for recirculating the digital values to be processed through the closed loop comprised by the logic circuit means and the delay line recirculating means in stepped time sequential relationship with the processing operations of the logic circuit means.
Claim 21
Dependent Claim
93 words
A digitally operable conversion apparatus according to claim 12 wherein the apparatus operates with binary coded decimal digits and the binary digits of the same decimal digit significance are time sequentially grouped together and the groupings interlaced in serially adjoining time relationship whereby processing operations of the arithmetic processing means on binary coded digits of corresponding decimal digit significance is facilitated, and said scaling means operates in known powers of 10 selectively to enter the conversion factor into the remainder register by ones, tens or hundreds for corresponding numbers of input signal pulses.
Claim 22
Dependent Claim
92 words
A digitally operable conversion apparatus according to claim 13 wherein said scaling means comprises delay shift register means having its input connected to the output of the arithmetic processing means and having its output selectively connected back to the input of said arithmetic processing means for delaying at least one of the binary coded decimal digital values sufficiently to increase its significance by at least one decimal point prior to resupplying the delayed value to the arithmetic processing means for entering into one of the remainder registers at a more significance value.
Claim 23
Dependent Claim
63 words
A digitally operable conversion apparatus according to claim 14 further comprising scale of 10 enabling circuit means operatively coupled to said delay shift register means and to the arithmetic processing means and responsive to build up in the count to be converted in a buffer storage means for entering values into the arithmetic unit whose significance has been increased by one decimal place.
Claim 24
Dependent Claim
64 words
A digitally operable conversion apparatus according to claim 15 further comprising scale of hundreds enabling circuit means operatively coupled to said delay shift regiSter means and to the arithmetic processing means and responsive to build up in the count to be converted in the buffer storage and means for entering values into the arithmetic unit whose significance has been increased by two decimal places.
Claim 25
Dependent Claim
155 words
A digitally operable conversion apparatus according to claim 16 further comprising a plurality of sets of preliminary storage and intermediate and delayed working flip-flop memory means interconnected with each other and with said arithmetic processing means and a buffer memory means for supplying signal pulses to be converted to an input of the arithmetic processing means in scales of units, tens or hundreds, the scale of 10 and scale of hundreds intermediate and delayed working flip-flop memory means being operatively coupled through the scale of 10 enabling circuit means and the scale of hundreds enabling circuit means, respectively, for enabling the arithmetic unit to process in the scale of 10 and hundreds, the preliminary storage flip-flop memory means serving to preliminarily store input data supplied thereto, and to supply the same to the intermediate and delayed working flip-flop memory means for use by the arithmetical processing means at an appropriate point in a processing cycle.
Claim 26
Dependent Claim
145 words
A digitally operable conversion apparatus according to claim 16 further comprising readout circuit means for selectively reading out the value stored in the major sum remainder register, said readout circuit means including complementing circuit means for reading out complemented numbers stored in the major sum remainder register, the complementing circuit means comprising complemented number sensing circuit means for sensing the existence of a complemented number stored in the major sum remainder register, complement enabling circuit means operatively coupled to said complement number sensing circuit means and to said arithmetic processing means for enabling the arithmetic processing means to subtract the complemented number from zero and to provide a true negative number at its output, and sign indicating circuit means responsive to the complemented number sensing circuit means for providing an output sign signal indicative of the negative character of a complemented number being read out.
Claim 27
Dependent Claim
136 words
A digitally operable conversion apparatus according to claim 18 wherein the complementing circuit means further includes bypass shift register means operatively coupled intermediate the input and output of the delay line recirculating means, bypass enabling circuit means responsive to said complemented number sensing circuit means for enabling said bypass shift register means to bypass a complemented number being read out around the arithmetic processing means and back into the input to the delay line recirculating means during a complementing readout operation, and bypass inhibiting circuit means responsive to the complemented number sensing circuit means and coupled intermediate the output of the arithmetic processing means and the input to the delay line recirculating means for preventing the true form of the complemented number from being read into the delay line recirculation means during a complementing read-out operation.
Claim 28
Dependent Claim
187 words
A digitally operable conversion apparatus according to claim 19 wherein the apparatus is capable of processing three different time sequential functions with each function corresponding to the processing operations performed with relation to one axis of a three orthogonal axes system and wherein each function is comprised of three words with each word forming the conversion factor integrand register, minor sum remainder register, and major sum remainder register, respectively, for a given function, the functions and words being arrayed on the delay line recirculating means in sequential time interlaced relationship in a manner such that the second word of a given function is occupied by the conversion factor integrand register of that function, the third word of the given function is occupied by The minor sum remainder register of that function, and the first word of the next succeeding function is occupied by major sum remainder register of the preceding function whereby all three functions are arrayed and continuously recirculated through the delay line recirculating means and interconnected logic circuit means in sequential time interlaced relationship by the timing circuit means, and improved processing speeds are obtained.
Claim 29
Dependent Claim
71 words
A digitally operable conversion apparatus according to claim 20 wherein there are three sets of input electric signal pulses, one for each of the three orthogonal axes and wherein each set of input signal pulses comprises the output signal pulses of an interferometer position measuring device for a respective axis, and means are provided for selectively changing the conversion factor stored in the integrand register for each of the three functions.
Claim 30
Dependent Claim
81 words
A digitally operable conversion apparatus according to claim 21 wherein the means for changing the conversion factor in the integrand register for each of the three functions includes sensing means for sensing an environmental condition effecting the accuracy of the interferometer measuring device, and automatic means responsive to the output of said sensing means for automatically changing the conversion factor in response to changes in the environmental condition in a manner so as to optimize the accuracy of the distance measurement.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-02 | 1976-07-03 | 1977-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-02 | 1980-07-03 | 1981-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-02 | 1984-07-03 | 1985-01-02 | $7700.00 | Window Closed / Lapsed |