US3707705A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory module
Assignee: Individual
•
Filing: 1967-12-20
•
Granted: 1972-12-26
•
Expires: 1987-12-20
Abstract
Abstract A core memory unit is disclosed using double card modules with each module having an X wire system common to both cards, and further having several Y wire systems, one per bit position (bit plane). The module holds decoders for X and Y wire systems, driven by a predecoder system common to all modules and external thereto. The Y wire systems operate with anticoincidence, the sense wire system is a double wire system, each wire being rectangularly looped as threaded through half of the cores of the bit locations of each bit position to suppress noise.
Inventors
- 👤 Jones V Howell Jr
- 👤 David W Mayne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:13
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/06; G11C11/06007; G11C11/06014; G11C11/06021; G11C11/06028; G11C11/06035
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
266 words
A memory unit comprising: a first and second printed circuit type module card; a first plurality of addressing lines, each affixed with opposite ends respectively to the first and second cards and extending across first and second areas respectively of the first and second cards and including lines crossing directly from one card to the respective other one; a second plurality of addressing lines arranged on the first card only to form an array of insulated intersections with the lines of the first plurality; a third plurality of addressing lines arranged on the second card only to form an array of insulated intersections with the lines of the first plurality; a plurality of bistable storage cells respectively coupled to the pairs of lines forming an intersection of the arrays; and circuit means on each of the cards including printed circuit lines for providing individual circuit paths to the lines of the pluralities; and including first circuit means on the first card connected to the lines of the second plurality to provide bit position distinguishing signals concurrently to several of the lines of the second plurality, each signal being dependent additionally on a bit value for the respective bit position; and including second circuit means on the second card connected to the lines of the third plurality to provide bit position distinguishing signals concurrently to several of the lines of the third plurality, each signal dependent additionally on a bit value for the respective bit position, all of the bit positions on the first card being different from all of the bit positions on the second card.
Claim 2
Dependent Claim
266 words
A memory unit comprising: a first and second printed circuit type module card; a first plurality of addressing lines, each affixed with opposite ends respectively to the first and second cards and extending across first and second areas respectively of the first and second cards and including lines crossing directly from one card to the respective other one; a second plurality of addressing lines arranged on the first card only to form an array of insulated intersections with the lines of the first plurality; a third plurality of addressing lines arranged on the second card only to form an array of insulated intersections with the lines of the first plurality; a plurality of bistable storage cells respectively coupled to the pairs of lines forming an intersection of the arrays; and circuit means on each of the cards including printed circuit lines for providing individual circuit paths to the lines of the pluralities; and including first circuit means on the first card connected to the lines of the second plurality to provide bit position distinguishing signals concurrently to several of the lines of the second plurality, each signal being dependent additionally on a bit value for the respective bit position; and including second circuit means on the second card connected to the lines of the third plurality to provide bit position distinguishing signals concurrently to several of the lines of the third plurality, each signal dependent additionally on a bit value for the respective bit position, all of the bit positions on the first card being different from all of the bit positions on the second card.
Claim 3
Dependent Claim
107 words
A memory unit as set forth in claim 1, the circuit means on each card including a first plurality of printed circuit bus lines, each connecting to a different plurality of one-half of the first plurality of addressing lines; and a second plurality of printed circuit bus lines, each connecting to a different plurality of the other half of the first plurality of addressing lines, so that each line of the first plurality is connected to a unique combination of bus lines of the first plurality on the first or the second car and of a bus line of the second plurality on the respective other card.
Claim 4
Dependent Claim
46 words
A memory unit as set forth in claim 1, the second and third pluralities being equal in number, each of the second and third pluralities of lines being organized in several groups, the number of lines per group being half the number of the first plurality.
Claim 5
Dependent Claim
42 words
A memory unit as set forth in claim 1, the lines of the second and third pluralities being organized in pairs, lines of each pair being serially interconnected, a pair of serial interconnected lines intersecting each line of the first plurality twice.
Claim 6
Dependent Claim
28 words
A memory unit as set forth in claim 1, second circuit contact means along an edge on each card for providing input connections to the first circuit means.
Claim 7
Dependent Claim
92 words
A memory unit as set forth in claim 1, the circuit means comprising: a bus system on each of the cards connected to the lines of the first plurality and including means for receiving control signals in pairs, one on each card so that one card of each module receives one control signal of the pair and the other card receives the respective other one of the pair, the bus system on each card including decoding means so that each pair of control signals energizes but one line of the first plurality.
Claim 8
Dependent Claim
53 words
A memory unit as in claim 1, wherein the bistable store cells are memory cores, and addressing lines include wires, the wires as part of the lines of the first plurality each being continuous as passing from one card to the other one and having the cores strung thereon, one core per intersection.
Claim 9
Dependent Claim
50 words
The unit as set forth in claim 1, comprising means interconnecting the cards for folding to obtain selectively different mutual orientation including a parallel, side by side position and in a substantially coplanar position, the lines of the first plurality being flexible at least where crossing over the interconnecting means.
Claim 10
Dependent Claim
17 words
A memory unit as set forth in claim 8, the means for interconnecting including a flexible hinge.
Claim 11
Dependent Claim
27 words
A memory unit as set forth in claim 8, comprising a pair of extraction levers linked to the cards for facilitating positioning and removal of the unit.
Claim 12
Dependent Claim
125 words
A memory unit as in claim 1, wherein the cells are individual magnetic cores, the addressing lines being wires traversing the cores, the wires of the first plurality continuously traversing cores of the plurality on card, crossing over to the other card and traversing cores of the plurality on the other card, the two cards interconnected by a flexible hinge, the memory unit further including decoder means distributed among the two cards and including a printed circuit bus system on each card establishing a first and a second decoder matrix, the rows of the first matrix and the columns of the second matrix being on one card, the columns of the first matrix and the rows of the second matrix being on the other card.
Claim 13
Dependent Claim
115 words
A memory unit as set forth in claim 11 the wires of the second and third pluralities being organized in groups, the wires of each group intersecting two cores on each wire of the first plurality, and being all on one of the cards; a first and a second plurality of bus lines for each group and on the respective one of the cards, the product of the first and second pluralities of bus lines being equal to the number of addressing lines of the group, each addressing line of the group connected to a unique combination of one of the first plurality of bus lines and one of the second plurality of bus lines.
Claim 14
Dependent Claim
27 words
A memory unit as set forth in claim 11, comprising printed circuit contacts on each card along the edge opposite to the edge of the interconnecting means.
Claim 15
Dependent Claim
275 words
A memory unit for digital data, the digital data being organized in words, each word comprising plurality bit groups, the memory unit being capable of storing N data words, each bit being stored in a bistable storage cell, comprising: a plurality memory modules, each for storing groups of N bits each, one group per word, each module being comprised of a printed circuit, two-card module, a card of a module of the Plurality respectively having storage cells for storing one-half of the number bits of each bit group stored in the module to which the card pertains; an array of X, Y addressing lines in each module for providing coincidence signals to the storage cells of the respective module, the Y lines organized in systems, there being as many Y line systems in each module as the bit groups stored in the module have bits, the X lines completing the input for the N storage cells for each bit to be stored in the module, the X lines extending from one card of a module of the plurality to the respective other card of the module; means for receiving addressing signals including connecting terminals on the cards and distinguishing among the N word locations of the unit and including decoder means on the cards for providing first addressing control signals in response to each addressing signal received; printed circuit lines on the cards connected to the decoder means for receiving the control signals and further connected for energizing a particular X line in each module; and means including printed circuit lines on the cards providing addressing control signals for each of said Y line systems.
Claim 16
Dependent Claim
275 words
A memory unit for digital data, the digital data being organized in words, each word comprising plurality bit groups, the memory unit being capable of storing N data words, each bit being stored in a bistable storage cell, comprising: a plurality memory modules, each for storing groups of N bits each, one group per word, each module being comprised of a printed circuit, two-card module, a card of a module of the Plurality respectively having storage cells for storing one-half of the number bits of each bit group stored in the module to which the card pertains; an array of X, Y addressing lines in each module for providing coincidence signals to the storage cells of the respective module, the Y lines organized in systems, there being as many Y line systems in each module as the bit groups stored in the module have bits, the X lines completing the input for the N storage cells for each bit to be stored in the module, the X lines extending from one card of a module of the plurality to the respective other card of the module; means for receiving addressing signals including connecting terminals on the cards and distinguishing among the N word locations of the unit and including decoder means on the cards for providing first addressing control signals in response to each addressing signal received; printed circuit lines on the cards connected to the decoder means for receiving the control signals and further connected for energizing a particular X line in each module; and means including printed circuit lines on the cards providing addressing control signals for each of said Y line systems.
Claim 17
Dependent Claim
46 words
A memory unit as in claim 14, each storage cell being a magnetizable core, the addressing lines including flexible wires, the X-line wires each extending from one card of a module to the respective other card thereof and having cores strung thereon, one core per intersection.
Claim 18
Dependent Claim
38 words
A memory unit as set forth in claim 14, the X line system on each module having two square matrix decoders, each distributed over the two cards for respectively addressing half of the X lines of the system.
Claim 19
Dependent Claim
23 words
A memory unit as set forth in claim 14, wherein the number of Y lines per module equals the number of X lines.
Claim 20
Dependent Claim
29 words
A memory unit as set forth in claim 14, wherein the Y line systems of a module each are connected to square-matrix decoder bus lines constituting the receiving means.
Claim 21
Dependent Claim
113 words
A memory unit as set forth in claim 14, the means for receiving addressing signals comprising: first circuit means external to the modules and responsive to a first portion of each of one addressing signal, and providing a pair of addressing control signals; a bus system on each of the cards connected to the X lines and to the first circuit means, so that one card of each module receives one control signal of the pair and the other card receives the respective other one of the pair, the bus system on each card including decoding means so that each pair of control signals energizes but one X addressing line of each module.
Claim 22
Dependent Claim
92 words
A memory unit as set forth in claim 19, including second circuit means external to the modules and responsive to the first portion of each of the addressing signals and providing a second pair of control signals; a second bus system on each of the cards connected to the X lines, and to the second circuit means analogous to connection of the first circuit means to the first bus system for energizing the respective X lines in the opposite sense; and circuit means for selectively operating the first and second circuit means.
Claim 23
Dependent Claim
105 words
A memory unit as set forth in claim 14, wherein the means for receiving include first circuit means external to the modules and being responsive to a particular portion of each of the addressing signals and producing as many pairs of control signals as a word has bits; a plurality of bus systems, one per Y line system so that each bus system of the plurality is respectively associated with a Y line system and on the same card as the respectively associated line system; each bus system respectively responsive to the pairs of control signals for energizing one Y line of each Y system.
Claim 24
Dependent Claim
30 words
A unit as set forth in claim 21, including means connected for controlling at least one control signal of each pair in accordance with a data word to be stored.
Claim 25
Dependent Claim
73 words
A unit aS set forth in claim 22, each Y line being disposed for providing inputs for two storage cells together with each X line, the first circuit means and the bus system for each Y line system being connected so that by operation of the polarity of the energizing signal one or the other of the two storage cells is energized, both being connected to the same X line being concurrently energized.
Claim 26
Dependent Claim
261 words
A memory unit comprising: a first and a second printed circuit card interconnected to permit selective folding to obtain a side by side position of the cards and an essentially coplanar position thereof; a first plurality of addressing lines, each strung for extending directly from the first card to the second card and continuing respectively over particular areas thereof, the lines being flexible at least where crossing over from the first card to the second card; a plurality of decoders, half of the plurality being disposed on the first card and respectively connected to half of the first plurality of lines, the remaining half of the plurality of decoders being disposed on the second card and being respectively connected to the remaining half of the lines; a second and a third plurality of addressing lines respectively disposed on the first and second cards for intersecting the line of the first plurality to form an array of storage places respectively defined by an insulated intersection of a line of the first plurality and a line of the second and third pluralities; a second and a third plurality of decoders respectively on the first and second cards and respectively connected to the lines of the second and third pluralities; a plurality of bistable storage cells disposed respectively at the intersections, each cell of the plurality being coupled to the lines respectively forming the intersection; and printed circuit means on the cards for connecting the decoders to printed circuit contacts along at least one particular edge of each of the first and second cards.
Claim 27
Dependent Claim
261 words
A memory unit comprising: a first and a second printed circuit card interconnected to permit selective folding to obtain a side by side position of the cards and an essentially coplanar position thereof; a first plurality of addressing lines, each strung for extending directly from the first card to the second card and continuing respectively over particular areas thereof, the lines being flexible at least where crossing over from the first card to the second card; a plurality of decoders, half of the plurality being disposed on the first card and respectively connected to half of the first plurality of lines, the remaining half of the plurality of decoders being disposed on the second card and being respectively connected to the remaining half of the lines; a second and a third plurality of addressing lines respectively disposed on the first and second cards for intersecting the line of the first plurality to form an array of storage places respectively defined by an insulated intersection of a line of the first plurality and a line of the second and third pluralities; a second and a third plurality of decoders respectively on the first and second cards and respectively connected to the lines of the second and third pluralities; a plurality of bistable storage cells disposed respectively at the intersections, each cell of the plurality being coupled to the lines respectively forming the intersection; and printed circuit means on the cards for connecting the decoders to printed circuit contacts along at least one particular edge of each of the first and second cards.
Claim 28
Dependent Claim
48 words
A memory unit as in claim 34, each storage cell being a magnetizable core, each addressing line including a wire on which the cores are strung, one core per intersection, the wires of the first plurality of addressing lines crossing from the first card to the second card.
Claim 29
Dependent Claim
172 words
A memory module comprising: a first and a second printed circuit card; an X-Y array addressing line system on each of said cards, defining a matrix of separated intersections of each Y-line of the system with each X-line of the system each line including a flexible wire; a plurality of magnetizable cores respectively connected to the X wire and the Y wire of the intersection; hinge means for connecting the first card to the second card; each of flexible wires of the X-lines respectively strung across the first card traversing plural cores of the plurality, continuing across the hinge means and traversing additional cores of the plurality on the second card, to form continuous X wire on both of the cards and as crossing the hinge means; first circuit means on the first and second cards respectively for completing an X-line addressing circuit for each X-line as it extends on both cards; and second circuit means on each card for completing a Y-line addressing circuit for the Y-lines on the respective card.
Claim 30
Dependent Claim
172 words
A memory module comprising: a first and a second printed circuit card; an X-Y array addressing line system on each of said cards, defining a matrix of separated intersections of each Y-line of the system with each X-line of the system each line including a flexible wire; a plurality of magnetizable cores respectively connected to the X wire and the Y wire of the intersection; hinge means for connecting the first card to the second card; each of flexible wires of the X-lines respectively strung across the first card traversing plural cores of the plurality, continuing across the hinge means and traversing additional cores of the plurality on the second card, to form continuous X wire on both of the cards and as crossing the hinge means; first circuit means on the first and second cards respectively for completing an X-line addressing circuit for each X-line as it extends on both cards; and second circuit means on each card for completing a Y-line addressing circuit for the Y-lines on the respective card.
Claim 31
Dependent Claim
23 words
A memory module as in claim 26, each storage cell being a magnetizable core traversed by the wires as pertaining to the lines.
Claim 32
Dependent Claim
141 words
A module as set forth in claim 26, the first circuit means includes: a first plurality of printed circuit bus lines on the first card; a second plurality of printed circuit bus lines on the second card; the printed circuit bus lines of the pluralities being connected to one-half of the plurality of said continuous X lines, in that like pluralities of the one-half of the plurality of X lines on the first card connect to each bus line of the first plurality and like pluralities of the one-half of the plurality of X lines on the second card connect to each bus line on the second plurality so that each of the one-half of the plurality contiguous X lines connects to a unique combination of one bus line of the first plurality and one bus line of the second plurality.
Claim 33
Dependent Claim
81 words
A module as set forth in claim 26, the first circuit means includes a second plurality of printed circuit bus lines on the first card respectively connected to the same X lines to which the bus lines of the first plurality connect, there being a pair of diodes connected in the respective connection between a bus line of the first plurality and a bus line of the second plurality on one hand, and the respective X lines on the other hand.
Claim 34
Dependent Claim
277 words
In a memory module a first printed circuit card having a first area for mounting magnetic cores; a first and a second plurality of respectively interspaced parallel wires extending across the first area; means for fastening one end only of each of the wires of the first and second pluralities of wires on the card; a first plurality of decoding means on a second area of the card; printed circuit etchings on the card for connecting the decoders of the first plurality respectively to ends of the wires of the first plurality; a plurality of printed circuit bus lines on a third area of the card; circuit means for connecting the ends to the second plurality to the bus lines; a third plurality of wires arranged on said first area, each wire of the third plurality being transverse to the wires of the first and second plurality, to form an array of intersections on the first area, each wire of the third plurality intersecting each wire of the first and second pluralities twice; a plurality of magnetizable cores respectively disposed at the intersections and being coupled to the wires forming the intersection; a second plurality of decoding means respectively connected to the wires of the third plurality; means on the card providing printed circuit signal paths from an edge of the card to the decoders of the pluralities and to the bus lines; and a second card similar constructed as the first card, the respective other ends of the wires of the first and second pluralities affixed to the second card, and connected to additional decoding means, completing the decoding means of the first and second pluralities.
Claim 35
Dependent Claim
277 words
In a memory module a first printed circuit card having a first area for mounting magnetic cores; a first and a second plurality of respectively interspaced parallel wires extending across the first area; means for fastening one end only of each of the wires of the first and second pluralities of wires on the card; a first plurality of decoding means on a second area of the card; printed circuit etchings on the card for connecting the decoders of the first plurality respectively to ends of the wires of the first plurality; a plurality of printed circuit bus lines on a third area of the card; circuit means for connecting the ends to the second plurality to the bus lines; a third plurality of wires arranged on said first area, each wire of the third plurality being transverse to the wires of the first and second plurality, to form an array of intersections on the first area, each wire of the third plurality intersecting each wire of the first and second pluralities twice; a plurality of magnetizable cores respectively disposed at the intersections and being coupled to the wires forming the intersection; a second plurality of decoding means respectively connected to the wires of the third plurality; means on the card providing printed circuit signal paths from an edge of the card to the decoders of the pluralities and to the bus lines; and a second card similar constructed as the first card, the respective other ends of the wires of the first and second pluralities affixed to the second card, and connected to additional decoding means, completing the decoding means of the first and second pluralities.
Claim 36
Dependent Claim
127 words
A memory module card as set forth in claim 30, each wire of the third plurality having a first and second portion, each intersecting all wires of the first and second pluralities. a first sense wire, coupled to the cores along the first portion only of each of the wires of third plurality in a manner that a portion of the sense wire runs along the two halves of a first portion of each of the wires of the third plurality in opposite direction as to any current flowing the respective wire of third plurality and the first sense wire; and a second sense wire coupled to the cores along the second portion only of each of the wires of the third plurality in an analogous manner.
Claim 37
Dependent Claim
150 words
A memory matrix having an X wire system, a Y wire system, and a plurality of cores, each one being in a matrix point and threaded through by an X wire of the system and by a Y wire of the system, comprising in combination: each Y wire of the system defining two matrix points with each X wire of the system, each Y wire being representative of two matrix columns; a pair of sense wires, a first sense wire of the pair traversing one-half of the cores along one Y matrix column each of every Y wire and in one direction and the respective other half of the cores along the respective Y column in the opposite direction in relation to any current flowing through the sense wire of the pair, the respective other sense wire traversing the cores along the respective other Y column of every Y wire.
Claim 38
Dependent Claim
150 words
A memory matrix having an X wire system, a Y wire system, and a plurality of cores, each one being in a matrix point and threaded through by an X wire of the system and by a Y wire of the system, comprising in combination: each Y wire of the system defining two matrix points with each X wire of the system, each Y wire being representative of two matrix columns; a pair of sense wires, a first sense wire of the pair traversing one-half of the cores along one Y matrix column each of every Y wire and in one direction and the respective other half of the cores along the respective Y column in the opposite direction in relation to any current flowing through the sense wire of the pair, the respective other sense wire traversing the cores along the respective other Y column of every Y wire.
Claim 39
Dependent Claim
247 words
A memory unit comprising: a first and a second printed cIrcuit card interconnected to permit selective folding to obtain a side by side position of the cards and angular position thereof; a first plurality of addressing lines, each strung for extending directly and continuously from the first card to the second card and respectively over particular areas thereof, the lines being flexible at least where crossing over from the first card to the second card; a second plurality of pluralities of addressing lines, distributed over the cards for intersecting the lines of the first plurality to form an array of storage places respectively defined by an insulated intersection of a line of the first plurality and a line of the second plurality; a pair of square matrix decoder systems, each of the two square matrix decoder systems having rows and columns, the rows and columns of each decoder system being distributed over the two cards, that the rows are on one card, the columns on the other; printed circuit lines on the cards for connecting the decoder systems to the lines of the first plurality; a decoder system for each of the second plurality of pluralities of addressing lines; printed circuit lines on the cards for connecting the decoder system to the addressing lines of the second plurality; and printed circuit lines including terminal connections along the edges of the cards, connected to the respective decoder systems for passing thereto addressing signals externally applied on the cards.
Claim 40
Dependent Claim
247 words
A memory unit comprising: a first and a second printed cIrcuit card interconnected to permit selective folding to obtain a side by side position of the cards and angular position thereof; a first plurality of addressing lines, each strung for extending directly and continuously from the first card to the second card and respectively over particular areas thereof, the lines being flexible at least where crossing over from the first card to the second card; a second plurality of pluralities of addressing lines, distributed over the cards for intersecting the lines of the first plurality to form an array of storage places respectively defined by an insulated intersection of a line of the first plurality and a line of the second plurality; a pair of square matrix decoder systems, each of the two square matrix decoder systems having rows and columns, the rows and columns of each decoder system being distributed over the two cards, that the rows are on one card, the columns on the other; printed circuit lines on the cards for connecting the decoder systems to the lines of the first plurality; a decoder system for each of the second plurality of pluralities of addressing lines; printed circuit lines on the cards for connecting the decoder system to the addressing lines of the second plurality; and printed circuit lines including terminal connections along the edges of the cards, connected to the respective decoder systems for passing thereto addressing signals externally applied on the cards.
Claim 41
Dependent Claim
40 words
A memory unit as in claim 33, each intersection having a magnetic core, the addressing lines each including a wire strung from the first card to the second card and having the cores mounted thereon for placement at the intersections.
Claim 42
Dependent Claim
23 words
A unit as set forth in claim 33, wherein each of the decoder systems for the second plurality is a square matrix decoder.
Claim 43
Dependent Claim
40 words
A unit as set forth in claim 33, wherein the number of addressing lines in each plurality of the second plurality are similar, and that number times the number constituting the second plurality equals the number of the first plurality.
Claim 44
Dependent Claim
242 words
A memory unit for digital data, the digital data being organized in words, each word comprising a plurality of bit groups, each group having a plurality of bits, the memory unit being provided for storing N data words, each bit being stored in a storage cell, comprising: a plurality of memory modules, each module being a unit for holding all of the storage cells for all bits of one bit group of all N words; an array of X and Y addressing lines in each module for providing addressing signals to the bit storage cells of the respective module, all of the Y lines of a module establishing a Y line system the Y line system organized in Y line subsystems, there being as many Y line subsystems in each module as the bit group stored in the module has bits; means in each module for receiving addressing signals, for selectively addressing one of the X lines of the array, the address signal being applied in parallel to all modules, each module separately decoding each of the addressing signal as received; and means for receiving a group of addressing signals, one pair per Y subsystem, for addressing one Y line per subsystem of the array on each module and including word address decoding means on each of the modules for operation in parallel on all modules, further including bit value distinguishing means for selectively operating the addressed Y line in each subsystem.
Claim 45
Dependent Claim
242 words
A memory unit for digital data, the digital data being organized in words, each word comprising a plurality of bit groups, each group having a plurality of bits, the memory unit being provided for storing N data words, each bit being stored in a storage cell, comprising: a plurality of memory modules, each module being a unit for holding all of the storage cells for all bits of one bit group of all N words; an array of X and Y addressing lines in each module for providing addressing signals to the bit storage cells of the respective module, all of the Y lines of a module establishing a Y line system the Y line system organized in Y line subsystems, there being as many Y line subsystems in each module as the bit group stored in the module has bits; means in each module for receiving addressing signals, for selectively addressing one of the X lines of the array, the address signal being applied in parallel to all modules, each module separately decoding each of the addressing signal as received; and means for receiving a group of addressing signals, one pair per Y subsystem, for addressing one Y line per subsystem of the array on each module and including word address decoding means on each of the modules for operation in parallel on all modules, further including bit value distinguishing means for selectively operating the addressed Y line in each subsystem.
Claim 46
Dependent Claim
33 words
A memory unit as set forth in claim 37, the modules each having matrix decoder means for receiving pairs of addressing signals, each pair uniquely addressing one of the X or Y lines.
Claim 47
Dependent Claim
17 words
A memory unit as set forth in claim 38, the matrix decoder means being square type matrices.
Claim 48
Dependent Claim
41 words
A memory unit as in claim 39, wherein each storage cell is a memory core, each module having two hinged cards, the X-lines of each module being wires, each wire extending across the two cards, the cores strung On these wires.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-26 | 1976-06-26 | 1976-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-26 | 1980-06-26 | 1980-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-26 | 1984-06-26 | 1984-12-26 | $7700.00 | Window Closed / Lapsed |