Compound inverter of variable output voltage and frequency

Claim 2

A polyphase inverter of variable output voltage having a direct current input and a polyphase alternating current output and comprising, in combination: a full voltage (FV) polyphase thyristor bridge connected to the poles of said direct current input respectively by noncapacitive impedances and with its a.c. side connected to said output terminals; an adjustable voltage (AV) polyphase thyristor bridge connected to the poles of said direct current input respectively by two series capacitors, hereinafter referred to as pulsing capacitors, with its a.c. side likewiSe directly connected to said output terminals, and further having a storage capacitor connected across its d.c. input, in series with said pulsing capacitors; diodes respectively connected in inverse polarity in parallel with each of the thyristors of said AV thyristor bridge; and control means adapted to provide a cyclical sequence of pulses for gating the respective thyristors of said AV bridge for inverting d.c. energy from said storage capacitor to polyphase a.c. energy at said output terminals and also adapted, at intervals determined by comparison of a voltage proportional to that across said storage capacitor with an adjustable reference voltage, to turn on alternatively thyristors of said FV bridge connected respectively to different output terminals and to different poles of said d.c. input, and thereby to charge one of said pulsing capacitors and then the other while concurrently causing the pulsing capacitor previously charged to discharge and to cause said storage capacitor to be charged when current, drawn through said inductor and a thyristor of said FV bridge as aforesaid, exceeds the requirements of a load connected to said output terminals, said control means being further adapted to turn on thyristors of said FV bridge at intervals and in sequence appropriate for turning off the respective thyristors of said AV bridge in said cyclical sequence.

Claim 3

A polyphase inverter as defined in claim 1 in which said non-capacitive impedances are provided by inductors.

Claim 4

A polyphase inverter as defined in claim 1 in which said non-capacitive impedances are provided by coupled inductor windings.

Claim 5

A polyphase inverter as defined in claim 3 in which clamping diode means are provided for preventing the voltage of said pulsing capacitors from exceeding that of the said d.c. input of the inverter.

Claim 6

A polyphase inverter as defined in claim 4 in which said clamping diode means includes two diodes, poled so as to be normally blocked by the voltage of said d.c. input of the inverter, cross connected respectively between the terminals of said storage capacitor and the opposite poles of said d.c. input.

Claim 7

A polyphase inverter as defined in claim 3 having, also, means for limiting the charging of said pulsing capacitors, said means being connected in parallel with said storage capacitor and consisting of a diode in series with an inductor winding coupled with said coupled inductor windings, said diode being poled to conduct current only when the voltage of said inductor winding exceeds, in the matching sense, the voltage across said storage capacitor.

Claim 8

A polyphase inverter as defined in claim 6 in which said inductor winding in series with said diode has substantially less turns than any of the other inductor windings coupled thereto.

Claim 9

A polyphase inverter as defined in claim 3 in which said control means is adapted to supplement each said turning on of a thyristor or thyristors of said FV bridge except said turnings on for turning off the respective thyristors of said AV bridge, by the subsequent turning on of an additional thyristor of said FV bridge connected to the same pole of said d.c. input as the thyristor or thyristors last previously turned on, thereby to assure substantially complete charging of said pulsing capacitors.

Claim 10

A polyphase inverter as defined in claim 8 in which said turning on of an additional thyristor is inhibited during operation of said inverter at relatively low output voltage.

Claim 11

A polyphase inverter as defined in claim 9 in which said control means are so arranged that said turning on of an additional thyristor is initiated by a signal produced by an additional winding coupled to said inductor windings but is not initiated when said signal occurs more than a predetermined time after the turning on of said thyristors last previously turned on.

Claim 12

A polyphase inverter as defined in claim 1 in which said voltage proportional to that across said storage capacitor for comparison wiTh said reference voltage is produced by means of an isolating circuit comprising: a source of alternating current of multikiloherz frequency; a series resistor; a diode rectifying bridge; a detector circuit; and a transformer having a first and a second winding, said first winding being connected to said diode bridge and said diode bridge being connected also in series with said series resistor across said storage capacitor in such a way that current flowing through said series resistor reduces the impedance to alternating currents in said winding rectified by said diode bridge, said second winding being connected to said detector circuit and said source so that said source causes alternating current to be drawn through said second winding in partially alternate paths that combine to produce a rectified current in a common path portion.

Claim 13

A three-phase inverter of variable frequency and output voltage adapted for operation with a direct current input of substantially fixed voltage, said inverter comprising, in combination: a full voltage (FV) three phase thyristor bridge with its d.c. input connected to the poles of said fixed voltage direct current input respectively by two coupled inductor windings and with its a.c. side directly connected to the output terminals of the inverter; an adjustable voltage (AV) three phase thyristor bridge with its d.c. input connected to the poles of said fixed voltage direct current input respectively by two series capacitors, hereinafter referred to as pulsing capacitors, with its a.c. side likewise directly connected to said output terminals, and further having a storage capacitor, of much greater magnitude than that of said pulsing capacitors, connected across its said d.c. input, in series with said pulsing capacitors; diodes respectively connected in inverse polarity in parallel with each of the thyristors of said AV thyristor bridge; control means adapted to provide a cyclical sequence of pulses, variable in frequency by a frequency control, for gating the respective thyristors of said AV bridge for inverting d.c. energy from said storage capacitor to three phase a.c. energy at said output terminals and also adapted, at intervals determined by comparison of a voltage proportional to that across said storage capacitor with a voltage adjusted as a function of the position of said frequency control, to turn on alternately thyristors of said FV bridge identified as hereinafter set forth by reference to the progress of said cyclical pulse sequence, and thereby to charge one and then the other of said pulsing capacitors by current passing through one of said inductor windings and through a load connected to said output terminals and concurrently causing the other of said capacitors to discharge through the same path; said thyristors alternately turned on as aforesaid being, in terms of output terminal connections and polarity of d.c. connections, at certain times, including the first time in the pending step of said cyclical sequence, either or both of those corresponding to the two thyristors of the same d.c. side of said AV bridge which are gated on during the said step and at other times, in alternation with said certain times, the thyristor corresponding to the other thyristor of said AV bridge which is gated on during said step; said control means including means to turn on during the terminal portion of each step of said cyclical sequence the thyristor of said FV bridge corresponding as aforesaid to the thyristor of said AV bridge that completes with such step its third consecutive step of on-gating and to assure that, prior to said terminal portion, the last previous turning on of said alternately turned on thyristors of said FV bridge is one that turned on the thyristor of said FV bridge corresponding to the thyristor of said AV bridge which is the only one on its d.c. side of said AV bridge which is gated on during said step.

Claim 14

A three-phase inverter of variable frequency and output voltage adapted for operation with a direct current input of substantially fixed voltage, said inverter comprising, in combination: a full voltage (FV) three phase thyristor bridge with its d.c. input connected to the poles of said fixed voltage direct current input respectively by two coupled inductor windings and with its a.c. side directly connected to the output terminals of the inverter; an adjustable voltage (AV) three phase thyristor bridge with its d.c. input connected to the poles of said fixed voltage direct current input respectively by two series capacitors, hereinafter referred to as pulsing capacitors, with its a.c. side likewise directly connected to said output terminals, and further having a storage capacitor, of much greater magnitude than that of said pulsing capacitors, connected across its said d.c. input, in series with said pulsing capacitors; diodes respectively connected in inverse polarity in parallel with each of the thyristors of said AV thyristor bridge; control means adapted to provide a cyclical sequence of pulses, variable in frequency by a frequency control, for gating the respective thyristors of said AV bridge for inverting d.c. energy from said storage capacitor to three phase a.c. energy at said output terminals and also adapted, at intervals determined by comparison of a voltage proportional to that across said storage capacitor with a voltage adjusted as a function of the position of said frequency control, to turn on alternately thyristors of said FV bridge identified as hereinafter set forth by reference to the progress of said cyclical pulse sequence, and thereby to charge one and then the other of said pulsing capacitors by current passing through one of said inductor windings and through a load connected to said output terminals and concurrently causing the other of said capacitors to discharge through the same path; said thyristors alternately turned on as aforesaid being, in terms of output terminal connections and polarity of d.c. connections, at certain times, including the first time in the pending step of said cyclical sequence, either or both of those corresponding to the two thyristors of the same d.c. side of said AV bridge which are gated on during the said step and at other times, in alternation with said certain times, the thyristor corresponding to the other thyristor of said AV bridge which is gated on during said step; said control means including means to turn on during the terminal portion of each step of said cyclical sequence the thyristor of said FV bridge corresponding as aforesaid to the thyristor of said AV bridge that completes with such step its third consecutive step of on-gating and to assure that, prior to said terminal portion, the last previous turning on of said alternately turned on thyristors of said FV bridge is one that turned on the thyristor of said FV bridge corresponding to the thyristor of said AV bridge which is the only one on its d.c. side of said AV bridge which is gated on during said step.

Claim 15

A thrEe phase inverter as defined in claim 12 in which said control means includes pull-up means whereby, after each turning on of a thyristor or thyristors of said FV bridge in alternation as there stated, an additional thyristor of the same d.c. side of said FV bridge as that or those last previously turned on is turned on to assure relatively complete charging of the pulsing capacitors.

Claim 16

A three phase inverter as defined in claim 13 in which said control means includes means for disabling the operation of said pull-up means during operation of said inverter at low output voltage.

Claim 17

A three phase inverter as defined in claim 14 in which the said disabling means includes means for comparing a fixed interval with the time required for storage and subsequent release of energy by either of said inductor windings, said last mentioned means including an additional inductor winding coupled to said previously mentioned inductor windings.

Claim 18

A three phase inverter as defined in claim 12 in which the means last mentioned in said claim 12 is adapted to determine during an interval preceding said terminal portion of said step, whether for the stated function of said last mentioned means an additional turning on of a thyristor of said FV bridge, in said alternating turn on sequence, is necessary, and in the event of such necessity to turn on such thyristor, regardless of the state of said storage capacitor at that time.

Claim 19

A three phase inverter as defined in claim 16 in which said control means includes means whereby each turning on of a thyristor or thyristors of said FV bridge in alternation as aforesaid, including the turning on of a thyristor during said interval preceding said terminal portion of said step, is supplemented by the subsequent turning on of an additional thyristor of the same d.c. side of said FV bridge as that or those last previously turned on, in order to assure relatively complete charging of the pulsing capacitors.

Claim 20

A three phase inverter as defined in claim 17 in which said control means is adapted to turn on said additional thyristor by turning on all thyristors of its d.c. side of said FV bridge.

Claim 21

A three phase thyristor bridge as defined in claim 17 in which an additional inductor winding coupled with said inductor windings is provided and said control means includes means associated with said additional inductor winding for the preventing the turning on of said additional thyristor when the time required for storage and release of energy by one of said first mentioned inductor windings exceeds a predetermined interval.

Claim 22

A three phase inverter as defined in claim 19 in which the said means associated with said additional inductor windings is further adapted upon unusually long duration of continued energy storage said first mentioned inductor windings, to turn on all thyristors of said FV bridge.

Claim 23

A three phase inverter as defined in claim 20 in which the entire inverter is protected by a single fuse or other circuit breaker adapted to break circuit at thrice the maximum safe current of a thyristor of said inverter, of the lowest current rating used in the event thyristors of different current rating are used, and thus to break circuit within the time required for said thrice thyristor maximum current to build up in said first mentioned inductor windings.

Claim 24

A three phase inverter as defined in claim 13 in which said control means includes means for providing a minimum interval between said alternate turning on of thyristors of said FV bridge, whereby current of said inverter is limited to a nondestructive value in the event of a lockup in said AV bridge or in the event of a short circuit in a load or other connections to the inverter output.

Claim 25

A three phase inverter as defined in claim 22 in which means are further provided for increasing said minimum interval when the storage and consequent release of energy by said inductor windings takes longer than a predetermined time commensurate with said minImum interval.

Claim 26

A three phase inverter as defined in claim 13 in which there is provided clamping means comprising two diodes, poled so as to be normally blocked by the voltage of said fixed voltage direct current input, cross connected respectively between the terminals of said storage capacitor and the opposite poles of said direct current input.

Claim 27

A three phase inverter as defined in claim 12 having, also, means for limiting the charging of said pulsing capacitors, and means being connected in parallel with said storage capacitor and consisting of a diode in series with an inductor winding coupled with said coupled inductor windings, said diode being poled to conduct current only when the voltage of said inductor winding exceeds, in the matching sense, the voltage across said storage capacitor.

Claim 28

A three phase inverter of variable frequency and output voltage adapted for operation with a direct current input of substantially fixed voltage, said inverter comprising in combination: a full voltage (FV) three phase thyristor bridge connected to the terminals of said direct current input respectively by two windings of an inductor and with its a.c. connections directly connected to the output terminals of the inverter; an adjustable voltage (AV) three phase thyristor bridge reactively connected to said direct current input respectively by two series capacitors, hereinafter referred to as pulsing capacitors, and with its a.c. connections likewise connected to said output terminals and further having a storage capacitor, of much greater magnitude than that of said pulsing capacitors, connected across its d.c. input, in series with said pulsing capacitors; diodes respectively connected in inverse polarity in parallel with each of the thyristors of said AV thyristor bridge; control means for adjusting the output frequency and voltage adapted to gate the thyristors of said bridges in sequence according to the following table, in which Roman numerals indicate the sequence of steps (periods) established by commutation of said AV bridge, arabic numbers less than 10 indicate AV bridge thyristors, numbers higher than 10 indicate FV bridge thyristors, odd numbers identify thyristors connected to one side of d.c. bridge input and even numbers those connected to the other input side, thyristors designated by numbers differing by 10 being connected to the same output terminal, as are also the pairs designated by an odd number and the next higher integer, and in which table rows are designated by capital letters, the letter A designating continuous on-gating except for a brief turn-off time preceding the end of the sequence step, B and C designating on-gating for the entire sequence step, D designating turn on of an FV thyristor during the terminal interval of the step for turning off an AV thyristor, E and F designating momentary turn-on in alternation at intervals determined by output voltage adjustment and load requirements, except that the last such turn on before said terminal interval may be provided regardless of load requirements, E further designating the first turn on of an FV thyristor in said step and F further designating the last such turn on prior to said terminal interval, the double designation in row E signifying that either or both of the designated thyristors may be so turned on: I II III IV V VI A 1 6 3 2 5 4 B 6 3 2 5 4 1 C 3 2 5 4 1 6 D 11 16 13 12 15 14 E 11,13 16,12 13,15 12,14 15,11 14,16 F 16 13 12 15 14 11

Claim 29

A three phase inverter of variable frequency and output voltage adapted for operation with a direct current input of substantially fixed voltage, said inverter comprising in combination: a full voltage (FV) three phase thyristor bridge connected to the terminals of said direct current input respectively by two windings of an inductor and with its a.c. connections directly connected to the output terminals of the inverter; an adjustable voltage (AV) three phase thyristor bridge reactively connected to said direct current input respectively by two series capacitors, hereinafter referred to as pulsing capacitors, and with its a.c. connections likewise connected to said output terminals and further having a storage capacitor, of much greater magnitude than that of said pulsing capacitors, connected across its d.c. input, in series with said pulsing capacitors; diodes respectively connected in inverse polarity in parallel with each of the thyristors of said AV thyristor bridge; control means for adjusting the output frequency and voltage adapted to gate the thyristors of said bridges in sequence according to the following table, in which Roman numerals indicate the sequence of steps (periods) established by commutation of said AV bridge, arabic numbers less than 10 indicate AV bridge thyristors, numbers higher than 10 indicate FV bridge thyristors, odd numbers identify thyristors connected to one side of d.c. bridge input and even numbers those connected to the other input side, thyristors designated by numbers differing by 10 being connected to the same output terminal, as are also the pairs designated by an odd number and the next higher integer, and in which table rows are designated by capital letters, the letter A designating continuous on-gating except for a brief turn-off time preceding the end of the sequence step, B and C designating on-gating for the entire sequence step, D designating turn on of an FV thyristor during the terminal interval of the step for turning off an AV thyristor, E and F designating momentary turn-on in alternation at intervals determined by output voltage adjustment and load requirements, except that the last such turn on before said terminal interval may be provided regardless of load requirements, E further designating the first turn on of an FV thyristor in said step and F further designating the last such turn on prior to said terminal interval, the double designation in row E signifying that either or both of the designated thyristors may be so turned on: I II III IV V VI A 1 6 3 2 5 4 B 6 3 2 5 4 1 C 3 2 5 4 1 6 D 11 16 13 12 15 14 E 11,13 16,12 13,15 12,14 15,11 14,16 F 16 13 12 15 14 11

Claim 30

A three phase inverter as defined in claim 26 in which said control means is adapted to gate the thyristors of said bridges in sequence according to the following table, in which the Roman numerals and rows, A, B,C,D,E and F have the same significance as in claim 26 and in which row G indicates a thyristor turned on following every turning on, except in said terminal interval, of the thyristors designated by row E, and row H indicates a thyristor turned on following every turning on of the thyristor designated by row F, in each case when the inductor of said coupled windings has delivered all or almost all of the energy it had just stored: I II III IV V VI A 1 6 3 2 5 4 B 6 3 2 5 4 1 C 3 2 5 4 1 6 D 11 16 13 12 15 14 E 11,13 16,12 13,15 12,14 15,11 14,16 F 16 13 12 15 14 11 G 15 1411161312H12 1514 11 16 13

Claim 31

A three phase inverter as defined in claim 27 in which said control means is adapted turn on thyristors as specified in rows G and H of the tabulation in said claim 27 only when the storing and release of energy by said inductor windings pursuant to turning on of thyristors designated respectively in row E or row F takes less than a predetermined period of time and in which turning on of said thyristors of said FV bridge is blocked during said predetermined period.

Claim 32

A three phase inverter as defined in claim 28 in which the time taken by the storage and release of energy by said inductor windings as aforesaid is determined by means of a sensing circuit including an additional inductor winding coupled to said first mentioned coupled inductor windings and in which said sensing circuit includes means for detecting abnormal duration of energy storage by said first mentioned inductor windings and, in response thereto, turning on all thyristors of said FV bridge and thereby relaxing the fusing or circuit breaker level and time requirements for protection of the inverter.

Claim 33

A three phase inverter as defined in claim 28 in which there is provided clamping means comprising two diodes, poled so as to be normally blocked by the voltage of said fixed voltage direct current input, cross connected respectively between the terminals of said storage capacitor and the opposite poles of said direct current input.

Claim 34

A three phase inverter as defined in claim 28 having, also, means for limiting the charing of said pulsing capacitors, and means being connected in parallel with said storage capacitor and consisting of a diode in series with an inductor winding coupled with said coupled inductor windings, said diode being poled to conduct current only when the voltage of said inductor winding exceeds, in the matching sense, the voltage across said storage capacitor.

Claim 35

A polyphase inverter of variable output voltage having a direct current input and a polyphase alternating current output and comprising, in combination: a full voltage (FV) polyphase thyristor bridge connected to the poles of said direct current input respectively by non-capacitive impedances and with its a.c. side connected to said output terminals; an adjustable voltage (AV) polyphase thyristor bridge connected to the poles of said direct current input respectively by two series capacitors, hereinafter referred to as pulsing capacitors, with its a.c. side likewise directly connected to said output terminals, and further having a storage capacitor connected across its d.c. input, in series with said pulsing capacitors; diodes respectively connected in inverse polarity in parallel with each of the thyristors of said AV thyristor bridge; and control means adapted to provide a cyclical sequence Of pulses for gating the respective thyristors of said AV bridge for inverting d.c. energy from said storage capacitor to polyphase a.c. energy at said output terminals and also adapted to turn on alternately thyristors of said FV bridge connected respectively to different output terminals and to different poles of said d.c. input, and thereby to charge one of said pulsing capacitors and then the other while concurrently causing the pulsing capacitor previously charged to discharge and to cause said storage capacitor to be charged when current, drawn through said inductor and a thyristor of said FV bridge as aforesaid, exceeds the requirements of a load connected to said output terminals, said control means being further adapted to turn on thyristors of said FV bridge at intervals and in sequence appropriate for turning off the respective thyristors of said AV bridge in said cyclical sequence.

Claim 36

A polyphase inverter of variable output voltage having a direct current input and a polyphase alternating current output and comprising, in combination: a full voltage (FV) polyphase thyristor bridge connected to the poles of said direct current input respectively by non-capacitive impedances and with its a.c. side connected to said output terminals; an adjustable voltage (AV) polyphase thyristor bridge connected to the poles of said direct current input respectively by two series capacitors, hereinafter referred to as pulsing capacitors, with its a.c. side likewise directly connected to said output terminals, and further having a storage capacitor connected across its d.c. input, in series with said pulsing capacitors; diodes respectively connected in inverse polarity in parallel with each of the thyristors of said AV thyristor bridge; and control means adapted to provide a cyclical sequence Of pulses for gating the respective thyristors of said AV bridge for inverting d.c. energy from said storage capacitor to polyphase a.c. energy at said output terminals and also adapted to turn on alternately thyristors of said FV bridge connected respectively to different output terminals and to different poles of said d.c. input, and thereby to charge one of said pulsing capacitors and then the other while concurrently causing the pulsing capacitor previously charged to discharge and to cause said storage capacitor to be charged when current, drawn through said inductor and a thyristor of said FV bridge as aforesaid, exceeds the requirements of a load connected to said output terminals, said control means being further adapted to turn on thyristors of said FV bridge at intervals and in sequence appropriate for turning off the respective thyristors of said AV bridge in said cyclical sequence.

Claim 37

A polyphase inverter of variable output voltage having a direct current input and a polyphase alternating current output at its output terminals and comprising, in combination: a full voltage (FV) polyphase thyristor bridge connected to the poles of said direct current input respectively by non-capacitive impedances and with its a.c. side connected to said output terminals; an adjustable voltage (AV) polyphase thyristor bridge connected to the poles of said direct current input respectively by two series capacitors, with its a.c. side likewise directly connected to said output terminals, and further having a storage capacitor connected across its d.c. input in between said series capacitors; and control means adapted to provide pulses for the gating on and off of the respective thyristors of said bridges for inverting d.c. energy to polyphase variable voltage a.c. energy at said output terminals.

Claim 38

A polyphase inverter of variable output voltage having a direct current input and a polyphase alternating current output at its output terminals and comprising, in combination: a full voltage (FV) polyphase thyristor bridge connected to the poles of said direct current input respectively by non-capacitive impedances and with its a.c. side connected to said output terminals; an adjustable voltage (AV) polyphase thyristor bridge connected to the poles of said direct current input respectively by two series capacitors, with its a.c. side likewise directly connected to said output terminals, and further having a storage capacitor connected across its d.c. input in between said series capacitors; and control means adapted to provide pulses for the gating on and off of the respective thyristors of said bridges for inverting d.c. energy to polyphase variable voltage a.c. energy at said output terminals.

Claim 41

A method as defined in claim 34 in which after each step of drawing current to increase the charge of said storage capacitor as aforesaid a supplemental pulse of current is drawn through the same inductor winding to complete the charge of the same pulsing capacitor without passing through said load by turning on another thyristor of said first thyristor bridge connected with said same inductor winding.

Claim 42

A method as defined in claim 34 in which a step of determining that the voltage across said storage capacitor is less than a reference voltage representative of said variable voltage preceds each step of drawing current to increase the charge of said storage capacitor.