Power regulating amplifier system

Claim 2

In combination: Limiter means for converting an input signal into a pulse train signal in which the pulses have substantially trapezoidal waveforms of uniform amplitude; a circuit adapted to receive said pulse train signal and responsive to a bias voltage, said circuit clipping said pulse train signal at a value in accordance with said bias voltage to vary the duty factor of said pulse train signal by an amount related to the rate of change of the edges of pulses in said pulse train signal; and detection means responsive to the magnitude of the power output of said circuit for comparing said magnitude with a reference signal to provide said bias voltage thereby varying the duty factor of said pulse train signal to maintain a substantially constant average power output of said circuit independently of variations in power supply voltages which energize said circuit.

Claim 3

The combinatioN according to claim 1 wherein said circuit has a symmetrical form for varying the duty cycle of both positive and negative pulse train signals.

Claim 4

The combination according to claim 2 wherein said symmetrical circuit comprises a first pair of transistors having their emitter terminals connected in circuit with a common terminal of a power supply, each of said transistors having their base terminals connected in circuit respectively with each of two terminals of a transformer winding symmetrically relative to a center tap of said winding, and said center tap being connected to receive said bias voltage.

Claim 5

The combination according to claim 3 in which clipped positive pulse train signals appear at the collector terminal of one of said transistors, and clipped negative pulse train signals appear at the collector terminal of the second of said first pair of transistors.

Claim 6

The combination according to claim 4 in which said symmetrical circuit further comprises a second pair of transistors symmetrically coupled to said first pair of transistors for further clipping said clipped positive and said clipped negative pulse train signals.

Claim 7

The combination according to claim 5 wherein said circuit further comprises a symmetrical amplifier for combining said positive and negative pulse train signals at a signal output terminal pair for applying said pulse train signals with a varied duty factor to a load.

Claim 8

The combination according to claim 6 in which said amplifier is a push-pull amplifier comprising power stages and driver stages for driving said power stages, said power stages being connected to the primary winding of an output transformer for coupling power into said transformer, said power supply voltage being applied between a center tap of said primary winding and a terminal of each of said power stages and said driver stages, and a second terminal of a driver stage being connected to a tap of said primary winding.

Claim 9

The combination according to claim 7 wherein a maximum current flows in said primary winding when a clipped portion of a pulse of said pulse train signals is applied to said amplifier, the voltage drop between said tap and an interconnection of said power stage with said primary winding during a flowing of said maximum current being substantially equal to the minimum supply voltage required by one of said driver stages to maintain relatively linear operation of said driver stage when said power stages are in a saturated non-linear mode of operation.

Claim 10

The combination according to claim 8 wherein the pulses of said input pulse train signal are portions of a sinusoid waveform, and a tuned transducer is interconnected at said output terminal pair to a secondary winding of said transformer for coupling power in a substantially sinusoidal waveform having a frequency equal to the frequency of said input sinusoidal waveform signal.

Claim 11

The combination according to claim 9 wherein said detection means further comprises an amplifier and filter for maintaining stable closed loop operation of said circuit and said detection means.

Claim 12

In combination: a transformer having a primary and a secondary winding; a supply of electrical power having a first terminal thereof connected to a turn of said primary winding; a first transistor having its collector-emitter terminals serially interconnected in circuit with a turn of said primary winding and a second terminal of said power supply; a second transistor having its collector-emitter terminals interconnected serially in circuit between the base terminal of said first transistor and a turn of said primary winding between the terminal of said power supply and said interconnection with said first transistor having a ratio with respect to the turns of said primary winding between the terminal of said power supply and the interconnection with said second transistor for supplying to said second transistor a minimum voltage necessary for maintaining substantially linear operation of said second Transistor during a period of time when said first transistor is saturated; a clipper circuit, the base terminal of said second transistor being connected to said clipper circuit and said secondary winding being connected to a load, said clipping circuit including means responsive to a bias signal for varying the clipping level; and a source of signal coupled to said clipper circuit, said source of signal including means for limiting an input signal to a substantially trapezoidal waveform.

Claim 13

In combination: a transformer having a primary and a secondary winding; a supply of electrical power having a first terminal thereof connected to a turn of said primary winding; a first transistor having its collector-emitter terminals serially interconnected in circuit with a turn of said primary winding and a second terminal of said power supply; a second transistor having its collector-emitter terminals interconnected serially in circuit between the base terminal of said first transistor and a turn of said primary winding between the terminal of said power supply and said interconnection with said first transistor having a ratio with respect to the turns of said primary winding between the terminal of said power supply and the interconnection with said second transistor for supplying to said second transistor a minimum voltage necessary for maintaining substantially linear operation of said second Transistor during a period of time when said first transistor is saturated; a clipper circuit, the base terminal of said second transistor being connected to said clipper circuit and said secondary winding being connected to a load, said clipping circuit including means responsive to a bias signal for varying the clipping level; and a source of signal coupled to said clipper circuit, said source of signal including means for limiting an input signal to a substantially trapezoidal waveform.

Claim 14

The combination according to claim 11 further comprising: a third transistor coupled to said primary winding in a circuit symmetrical to the coupling of said first transistor to said primary winding; a fourth transistor coupled to said third transistor in a circuit symmetrical to said interconnection of said second transistor with said first transistor; and means for connecting said source of signal in a symmetrical fashion to the base terminal of said fourth transistor.