Beam intensity control for different writing rates in a display system

Claim 2

In a digitally-controlled display system of the type in which a display is formed on a display surface of a display tube containing a deflectable beam whose intensity is controllable by producing a succession of strokes, each stroke being formed by deflecting the unblanked beam from a selected stroke start point on said surface to a selected stroke end point, each stroke being formed during a fixed clock period, with the strokes being of varying lengths, the system further including data containing means which contain data related to the length of each stroke along a first axis and its length along a second orthogonal axis, an arrangement for controlling the beam intensity as a function of stroke length, comprising: first means for utilizing during each clock period the length data along said first and second axes of a stroke to be formed during said clock period and for estimating the stroke''s length between its start and end points, the estimated length definable as L being a function of k(X/2 + Y/2 + P/2), wherein X represents the stroke''s length along said first axis, Y represents the stroke''s length along said second axis, P is the greater of X or Y and k is a constant; and second means for utilizing the estimated stroke length for controlling the intensity of said beam as it is deflected from the stroke''s start point to its end point.

Claim 3

The arrangement as recited in claim 1 wherein k 1.

Claim 4

The arrangement as recited in claim 1 wherein k 0.94.

Claim 5

The arrangement as recited in claim 1 wherein said data containing means contain the stroke''s length data along said X and Y axes in digital form and said first means include buffer means for receiving the stroke''s length data along each axis from said data containing means and for holding it during the period when said beam is deflected from the stroke''s start point to its end point, and said first means further include converting means for converting said data in said second means during said period into related analog signals.

Claim 6

The arrangement as recited in claim 4 wherein said first means include estimating means coupled between said converting means and said second means for providing the latter with an input potential which is a function of the estimated stroke length.

Claim 7

The arrangement as recited in claim 4 wherein said converting means include a first converter for providing an analog signal which is a function of the stroke''s length along the X axis and a second converter for providing an analog signal which is a function of the stroke''s length along the Y axis, said first means further including estimating means coupled to said first and second converters and further coupled to said second means at a junction point, for providing at said junction point a potential which is a function of the estimated stroke length.

Claim 8

The arrangement as recited in claim 6 wherein said estimating means comprises first, second and third resistors, said first resistor being connected between saId first converter and said junction point, said third resistor being connected between said junction point and said second converter, said second resistor having one end coupled to said junction point, and diode means for coupling the other end of said second resistor to said first and second converters, whereby when the analog signal from said first converter is greater than the analog signal from said second converter, said first and second resistors are effectively in parallel and when the analog signal from said second converter is greater than the analog signal from said first converter said second and third resistors are effectively in parallel.

Claim 9

The arrangement as recited in claim 7 wherein said diode means include first, second and third diodes with their cathodes connected together at a common point, the anodes of said first and second diodes being respectively connected to said first and second converters, the anode of said third diode being connected to said other end of said second resistor and means for maintaining said third diode in a forward biased state.

Claim 10

The arrangement as recited in claim 8 wherein k 1 when the potential at said junction point is directly applied to said second means.

Claim 11

The arrangement as recited in claim 8 further including variable resistive means at said junction point for controlling the percentage of the potential at said junction point which is applied to said second means to thereby control the value of k to be less than 1.

Claim 12

In combination with a display unit of the type which includes a beam which is deflectable on a display surface from one point to another to form a stroke therebetween, the unit including means which are responsive to a beam intensity control signal to control the beam intensity, and a symbol data storage unit which contains the deflection rates of each stroke of a symbol to be displayed in terms of the stroke''s length along two orthogonal axes of said display surface, said axes being definable as X and Y, said unit being clockable by a clock pulse of a sequence of clock pulses supplied thereto to supply said display unit with the stroke''s deflection rates in said X and Y axes so as to deflect said beam from the stroke''s start point to its end point, an arrangement for controlling the intensity of said beam as it is deflected to form said stroke, the arrangement comprising: first means for receiving from said storage unit the deflection rates of said stroke along said X and Y axes and for converting said rates into a potential at an output junction of said first means, said potential being a function of k(X/2 + Y/2 + P/2), wherein X represents the stroke''s X deflection rate, Y represents the stroke''s Y deflection rate, P is the greater of X or Y and k is a constant; and second means for utilizing said potential to provide a beam intensity control signal to said display unit, said control signal being a function of the amplitude of said potential.

Claim 13

In combination with a display unit of the type which includes a beam which is deflectable on a display surface from one point to another to form a stroke therebetween, the unit including means which are responsive to a beam intensity control signal to control the beam intensity, and a symbol data storage unit which contains the deflection rates of each stroke of a symbol to be displayed in terms of the stroke''s length along two orthogonal axes of said display surface, said axes being definable as X and Y, said unit being clockable by a clock pulse of a sequence of clock pulses supplied thereto to supply said display unit with the stroke''s deflection rates in said X and Y axes so as to deflect said beam from the stroke''s start point to its end point, an arrangement for controlling the intensity of said beam as it is deflected to form said stroke, the arrangement comprising: first means for receiving from said storage unit the deflection rates of said stroke along said X and Y axes and for converting said rates into a potential at an output junction of said first means, said potential being a function of k(X/2 + Y/2 + P/2), wherein X represents the stroke''s X deflection rate, Y represents the stroke''s Y deflection rate, P is the greater of X or Y and k is a constant; and second means for utilizing said potential to provide a beam intensity control signal to said display unit, said control signal being a function of the amplitude of said potential.

Claim 14

The arrangement as recited in claim 11 wherein the X and Y deflection rates from said storage unit are in digital form, said first means include a first buffer for receiving the stroke''s X deflection rate from said storage unit and a second buffer for receiving the stroke''s Y deflection rate from said storage unit, first and second digital-to-analog converters coupled to said first and second buffers for converting the digital stroke''s deflection rates in said buffers into related X and Y analog signals, and stroke length estimator means for providing said potential as a function of said X and Y analog signals.

Claim 15

The arrangement as recited in claim 12 further including delay means responsive to said clock pulse for providing said first and second buffers with a delayed activating clOck pulse to activate said buffers to receive said X and Y deflection rates from said storage unit and to hold said rates therein until a subsequent delayed activating clock pulse is applied thereto.

Claim 16

The arrangement as recited in claim 12 wherein said stroke length estimator means comprises first, second and third resistors, said first resistor being connected between said first converter and said junction point, said third resistor being connected between said junction point and said second converter, said second resistor having one end coupled to said junction point, and diode means for coupling the other end of said second resistor to said first and second converter, whereby when the analog signal from said first converter is greater than the analog signal from said second converter, said first and second resistors are effectively in parallel and when the analog signal from said second converter is greater than the analog signal from said first converter said second and third resistors are effectively in parallel.

Claim 17

The arrangement as recited in claim 14 wherein said diode means include first, second and third diodes with their cathodes connected together at a common point, the anodes of said first and second diodes being respectively connected to said first and second converters, the anode of said third diode being connected to said other end of said second resistor and means for maintaining said third diode in a forward biased state.

Claim 18

The arrangement as recited in claim 15 wherein k 1 when the potential at said junction point is directly applied to said second means.

Claim 19

The arrangement as recited in claim 15 further including delay means responsive to said clock pulse for providing said first and second buffers with a delayed activating clock pulse to activate said buffers to receive said X and Y deflection rates from said storage unit and to hold said rates therein until a subsequent delayed activating clock pulse is applied thereto.

Claim 20

The arrangement as recited in claim 17 wherein k 1 when the potential at said junction point is directly applied to said second means.

Claim 21

The arrangement as recited in claim 17 further including variable resistive means at said junction point for controlling the percentage of the potential at said junction point which is applied to said second means to thereby control the value of k to be less than 1.