Synchronous parallel counter with common steering of clock pulses to binary stages
Abstract
Abstract PARALLEL COUNTER CONSTRUCTED AS AN INTEGRATED CIRCUIT WITH A PLURALITY OF PAIRS OF NAND GATES FORMING BINARY STAGES, AND A STEERING CIRCUIT INCLUDING INPUT NAND GATES ASSOCIATED WITH THE BINARY STAGES. THE STEERING CIRCUIT INCLUDES COUPLING FROM THE OUTPUTS OF THE BINARY STAGES TO THE INPUTS OF THE HIGHER ORDER INPUT NAND GATE, AND ALSO COUPLINGS FROM THE OUTPUTS OF THE INPUT NAND GATES TO RESET INPUTS OF THE LOWER ORDER BINARY STAGES. THE CLOCK PULSES MAY OR MAY NOT BE PERIODIC AND MAY HAVE DIFFERENT PULSE DURATIONS, AND AN INPUT CIRCUIT COUPLED TO ALL OF THE INPUT NAND GATES DISABLES THE SAME AT A PREDETERMINED TIME AFTER THE BEGINNING OF EACH CLOCK PULSE. A RESET GATE IS COUPLED TO THE RESET INPUT OF THE HIGHEST ORDER BINARY STAGE TO RESET THE COUNTER AT THE DESIRED COUNT.
Inventors
- 👤 John R Reinert
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-12 | 1976-06-12 | 1976-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-12 | 1980-06-12 | 1980-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-12 | 1984-06-12 | 1984-12-12 | $7700.00 | Window Closed / Lapsed |