Automatic re-engage circuit for an electronic speed control system

Claim 2

A speed control system for an automotive vehicle having power means for moving the vehicle at varying or constant speeds comprising sensing means responsive to the speed of the vehicle for generating an output signal related to said speed; memory means connected to the sensing means, the memory means being operative when enabled for memorizing the speed of the vehicle as represented by the output signal of the sensing means; means connected to the memory means for enabling the latter when the vehicle is at the desired speed; speed error detecting means connected to the memory means and responsive to the variation of the speed of the vehicle from the memorized speed for generating an output signal related to said variations; actuating means connected to the speed error detecting means and the power means and responsive to the output signal of the speed error detecting means for controlling the power means in a speed maintaining manner; means for disabling the actuating means to allow the vehicle speed to decrease below the memorized speed; bistable circuit means shiftable between first and second states connected to the speed error detecting means and responsive to the output signal thereof for changing from the first state to the second state when the vehicle is at a predetermined speed less than the memorized speed; and circuit means connected to the bistable circuit means, the speed Error detecting means and the actuating means and responsive to the output signal of the speed error detecting means and the state of the bistable means for enabling the actuating means to again control the power means in a speed maintaining manner when the bistable means is in the second state and the speed of the vehicle is increased to the memorized speed.

Claim 3

A speed control system for a throttle control automotive vehicle comprising sensing means responsive to the speed of the vehicle for generating an output signal related to said speed; memory means connected to the sensing means, the memory means being operative when enabled for memorizing the speed of the vehicle as represented by the output signal of the sensing means; speed error detecting means connected to the memory means and responsive to the variations of the speed of the vehicle from a memorized speed for generating an output signal related to said variations; actuating means connected to the speed error detecting means and the throttle and responsive to the output signal of the speed error detecting means for operating the throttle in a speed maintaining manner when the actuating means is supplied with operating power; a source of power; latching means connected to the actuating means and to the source of power for supplying power to the actuating means when the latching means is latched; engaging means connected to the memory means and to the latching means for enabling the memory means and latching the latching means when the vehicle is at the desired speed; means for unlatching the latching means to allow the vehicle to decrease below the memorized speed; bistable circuit means shiftable between first and second states connected to the speed error detecting means and responsive to the output signal thereof for changing from the first state to the second state when the vehicle is at a predetermined speed less than the memorized speed; circuit means connected to the bistable circuit means, the speed error detecting means and the latching means and responsive to the output signal of the speed error detecting means and the state of the bistable means for latching the latching means so as to enable the actuating means to again operate the throttle in a speed maintaining manner when the bistable means is in the second state and the speed of the vehicle is increased to the memorized speed; and means connected to the bistable circuit means and the latching means for shifting the bistable circuit means from the second state to the first state when the latching means is latched.

Claim 4

A speed control system for a throttle control automotive vehicle comprising sensing means responsive to the speed of the vehicle for generating an output signal related to said speed; memory means connected to the sensing means, the memory means being operative when enabled for memorizing the speed of the vehicle as represented by the output signal of the sensing means; speed error detecting means connected to the memory means and responsive to the variations of the speed of the vehicle from a memorized speed for generating an output signal related to said variations; actuating means connected to the speed error detecting means and the throttle and responsive to the output signal of the speed error detecting means for operating the throttle in a speed maintaining manner when the actuating means is supplied with operating power; a source of power; latching means connected to the actuating means and to the source of power for supplying power to the actuating means when the latching means is latched; engaging means connected to the memory means and to the latching means for enabling the memory means and latching the latching means when the vehicle is at the desired speed; means for unlatching the latching means to allow the vehicle to decrease below the memorized speed; bistable circuit means shiftable between first and second states connected to the speed error detecting means and responsive to the output signal thereof for changing from the first state to the second state when the vehicle is at a predetermined speed less than the memorized speed; circuit means connected to the bistable circuit means, the speed error detecting means and the latching means and responsive to the output signal of the speed error detecting means and the state of the bistable means for latching the latching means so as to enable the actuating means to again operate the throttle in a speed maintaining manner when the bistable means is in the second state and the speed of the vehicle is increased to the memorized speed; and means connected to the bistable circuit means and the latching means for shifting the bistable circuit means from the second state to the first state when the latching means is latched.

Claim 5

A speed control system for a throttle controlled automotive vehicle comprising sensing means responsive to the speed of the vehicle for generating an output signal related to said speed; memory means connected to the sensing means, the memory means being operative when enabled for memorizing the speed of the vehicle as represented by the output signal of the sensing means; speed error detecting means connected to the memory means and responsive to the variations of the speed of the vehicle from a speed memorized by the memory means for generating an output signal related to said variations; actuating means connected to the speed error detecting means and the throttle and responsive to the output signal of the speed error detecting means for operating the throttle in a speed maintaining manner when said actuating means is supplied with operating power; a source of power; first latching means connected to the source of power and the actuating means for supplying operating power to the actuating means when said latching means is latched; engaging means connected to the memory means, the actuating means and the source of power for enabling the memory and latching the first latching means when the vehicle is at the desired speed, the actuating means being responsive to the output signal of the speed error detecting means for operating the throttle so as to maintain said speed; means for unlatching the first latching means to alloW the vehicle speed to decrease below the memorized speed; bistable circuit means shiftable between first and second states connected to the speed error detecting means and responsive to the output signal thereof for changing from the first state to the second state when the vehicle is at a predetermined speed less than the memorized speed; circuit means connected to the bistable circuit means, the speed error detecting means and the first latching circuit and responsive to the output signal of the speed error detecting means and the state of the bistable means for latching the first latching means when the bistable means is in the second state, the speed of the vehicle is increased to the memorized speed and the circuit means is supplied with operating power; second latching means connected to the source of power and the circuit means for supplying operating power to the circuit means when said second latching means is latched; and automatic re-engage means connected to the memory means, the first latching means and the second latching means for enabling the memory means and latching the first and second latching means so as to supply operating power to the actuating means and the circuit means, whereby the speed control system is operative upon the actuation of the engage means at the desired speed for maintaining the vehicle at the desired speed and is operative when the automatic re-engage means is actuated at the desired speed for maintaining the vehicle at the desired speed and for automatically re-engaging the speed control system when the first latching means is disabled and the vehicle has decreased to a predetermined speed less than the memorized speed and is then accelerated to the memorized speed.

Claim 6

A speed control system for a throttle controlled automotive vehicle comprising sensing means responsive to the speed of the vehicle for generating an output signal related to said speed; memory means connected to the sensing means, the memory means being operative when enabled for memorizing the speed of the vehicle as represented by the output signal of the sensing means; speed error detecting means connected to the memory means and responsive to the variations of the speed of the vehicle from a speed memorized by the memory means for generating an output signal related to said variations; actuating means connected to the speed error detecting means and the throttle and responsive to the output signal of the speed error detecting means for operating the throttle in a speed maintaining manner when said actuating means is supplied with operating power; a source of power; first latching means connected to the source of power and the actuating means for supplying operating power to the actuating means when said latching means is latched; engaging means connected to the memory means, the actuating means and the source of power for enabling the memory and latching the first latching means when the vehicle is at the desired speed, the actuating means being responsive to the output signal of the speed error detecting means for operating the throttle so as to maintain said speed; means for unlatching the first latching means to alloW the vehicle speed to decrease below the memorized speed; bistable circuit means shiftable between first and second states connected to the speed error detecting means and responsive to the output signal thereof for changing from the first state to the second state when the vehicle is at a predetermined speed less than the memorized speed; circuit means connected to the bistable circuit means, the speed error detecting means and the first latching circuit and responsive to the output signal of the speed error detecting means and the state of the bistable means for latching the first latching means when the bistable means is in the second state, the speed of the vehicle is increased to the memorized speed and the circuit means is supplied with operating power; second latching means connected to the source of power and the circuit means for supplying operating power to the circuit means when said second latching means is latched; and automatic re-engage means connected to the memory means, the first latching means and the second latching means for enabling the memory means and latching the first and second latching means so as to supply operating power to the actuating means and the circuit means, whereby the speed control system is operative upon the actuation of the engage means at the desired speed for maintaining the vehicle at the desired speed and is operative when the automatic re-engage means is actuated at the desired speed for maintaining the vehicle at the desired speed and for automatically re-engaging the speed control system when the first latching means is disabled and the vehicle has decreased to a predetermined speed less than the memorized speed and is then accelerated to the memorized speed.