Monitor for timing circuits

Claim 2

A timing and monitor circuit comprising: timing means for producing periodic output pulses having preset time durations and preset spacings therebetween; first and second delay circuits, the first delay circuit exhibiting a time delay greater than said preset time duration, and said second delay circuit exhibiting a time delay greater than the period of time corresponding to said preset spacings, each of said delay circuits being responsive to input signals having a time duration greater than its time delay for producing output signals; circuit means coupling said first and second time delay circuits to said timing means so that the pulses applied to said second delay circuit are inverted with respect to those applied to said first delay circuit; a latching circuit coupled to said first and second delay circuits for producing a continuous alarm signal in response to an output signal from said delay circuits, and circuit means for resetting said latching circuit.

Claim 3

A circuit as defined in claim 1 including: disable means for disabling said monitor circuit from responding to timing pulses.

Claim 4

A circuit as defined in claim 1 including: circuit means coupled to said delay circuit for adjusting said time delays.

Claim 5

A timing and monitor circuit comprising: timing means for producing periodic pulses having preset time durations and preset spacings therebetween; a pair of signal translating circuits; circuit means coupling said timing means to the inputs of said translating circuits so that the signals applied to the inputs of said translating circuits are inverted with respect to each other; circuit means coupled to one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least said preset time duration; circuit means coupled to the other one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least a period corresponding to said preset spacings, and circuit means coupled to the output of said pair of translating circuits for producing an alarm signal in response to an output signal from said translating circuits.

Claim 6

A timing and monitor circuit comprising: timing means for producing periodic pulses having preset time durations and preset spacings therebetween; a pair of signal translating circuits; circuit means coupling said timing means to the inputs of said translating circuits so that the signals applied to the inputs of said translating circuits are inverted with respect to each other; circuit means coupled to one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least said preset time duration; circuit means coupled to the other one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least a period corresponding to said preset spacings, and circuit means coupled to the output of said pair of translating circuits for producing an alarm signal in response to an output signal from said translating circuits.

Claim 7

A circuit as defined in claim 4 wherein: said circuit means coupled to the output of said translating circuits comprises a latching circuit for providing a continuous signal in response to an output signal from said translating circuits, and circuit means for resetting said latching circuit.

Claim 8

A circuit as defined in claim 4 wherein: said translating circuits comprise gate circuits, and said inhibiting circuit means coupled to said translating circuits includes capacitive means providing a charging circuit for delaying the response of the gate circuits to the input signals.

Claim 9

A circuit as defined in claim 4 wherein: said timing means provides a pair of output signals wherein one signal is the inverse of the other, and said circuit means coupling said timing means to said translating circuits couples individual ones of said pair of output signals to separate inputs of said translating circuits.

Claim 10

A circuit as defined in claim 4 wherein: said circuit means coupling said timing means to said translating circuit applies said Periodic pulses to one of said translating circuits and inverts said periodic pulses prior to applying them to said other translating circuit.

Claim 11

A circuit for monitoring the operation of a timing circuit producing periodic pulses having preset time durations and preset spacings therebetween comprising: a pair of signal translating circuits; circuit means coupling the timing circuit to the inputs of said translating circuits so that the signals applied to the inputs of said translating circuits are inverted with respect to each other; capacitive means for providing a charging circuit coupled to one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least said preset time duration; capacitive means for providing a charging circuit coupled to the other one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least a period corresponding to said preset spacings; circuit means for adjusting the values of said capacitive means, and circuit means coupled to the output of said pair of translating circuits for producing an alarm signal in response to an output signal from said translating circuits.

Claim 12

A circuit for monitoring the operation of a timing circuit producing periodic pulses having preset time durations and preset spacings therebetween comprising: a pair of signal translating circuits; circuit means coupling the timing circuit to the inputs of said translating circuits so that the signals applied to the inputs of said translating circuits are inverted with respect to each other; capacitive means for providing a charging circuit coupled to one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least said preset time duration; capacitive means for providing a charging circuit coupled to the other one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least a period corresponding to said preset spacings; circuit means for adjusting the values of said capacitive means, and circuit means coupled to the output of said pair of translating circuits for producing an alarm signal in response to an output signal from said translating circuits.

Claim 13

A circuit as defined in claim 9 wherein: said capacitive means includes a plurality of capacitors, and said control circuit means includes means for selecting at least one of said capacitors to control the duration of said inhibit period.

Claim 14

A circuit as defined in claim 9 wherein: said capacitive means is electrically variable, and said control circuit means controls the value of said capacitive means.

Claim 15

A circuit as defined in claim 9 including: a disable circuit for selectively disabling said monitor circuit from responding to the timing signals.

Claim 16

A circuit for monitoring the operation of a timing circuit producing periodic pulses having preset time durations and preset spacings therebetween comprising: a pair of signal translating circuits; circuit means coupling the timing circuit to the inputs of said translating circuits so that the signals applied to the inputs of said translating circuits are inverted with respect to each other; capacitive means for providing a charging circuit coupled to one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least said preset time duration; capacitive means for providing a charging circuit coupled to the other one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least a period corresponding to said preset spacings, and circuit means coupled to the output of said pair of translating circuits for producing a signal in response to an output signal from said translating circuits.

Claim 17

A circuit for monitoring the operation of a timing circuit producing periodic pulses having preset time durations and preset spacings therebetween comprising: a pair of signal translating circuits; circuit means coupling the timing circuit to the inputs of said translating circuits so that the signals applied to the inputs of said translating circuits are inverted with respect to each other; capacitive means for providing a charging circuit coupled to one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least said preset time duration; capacitive means for providing a charging circuit coupled to the other one of said translating circuits for inhibiting said circuit from producing an output signal in response to an input signal for at least a period corresponding to said preset spacings, and circuit means coupled to the output of said pair of translating circuits for producing a signal in response to an output signal from said translating circuits.