Transistor circuit performing gating operation

Claim 2

A transistor circuit for performing a gating operation, comprising signal transmitting means for transmitting a signal from an input terminal to an output terminal, signal shunting means connected to said transmitting means between said input and output terminals and including at least a first switching transistor having a collector, emitter and base and through which a shunt path for the input signal is provided when said first switching transistor is in its on state, signal source means providing a gating signal, transistor control means receiving said gating signal and selectively conditioning said first switching transistor in said on state and in the off state thereof in correspondence with said gating signal, and bias voltage applying means applying bias voltages to both said collector and emitter of said first switching transistor to ensure that said transistor is completely inactive when in said off state.

Claim 3

A transistor circuit according to claim 1, in which said bias voltages applied to said collector and emitter, respectively, of the first switching transistor have the same potential.

Claim 4

A transistor circuit according to claim 1, in which said bias voltage applying means has two terminals respectively connected to said collector and emitter of the first switching transistor and at which the same DC voltages appear.

Claim 5

A transistor circuit according to claim 1, in which said transmitting means includes impedance means between said input and output terminals, and said shunting means is connected to said transmitting means between said impedance means and said output terminal.

Claim 6

A transistor circuit according to claim 1, in which said transistor control means includes a second switching transistor connected to said first switching transistor to condition the latter in said on and off states thereof in response to said second switching transistor being in its off and on states, respectively, said off and on states of said second switching transistor being controlled by said gating signal.

Claim 7

A transistor circuit according to claim 5, in which said first and second switching transistors are of the same type, the collector-emitter path of said first switching transistor defines said shunt path when said first switching transistor is in said on state, means apply a bias voltate to the base of said first switching transistor for conditioning the latter in said on state, the collector-emitter path of said second switching transistor is connected between said base of the first switching transistor and ground so as to remove the bias voltage from said base of the first switching transistor and turn the latter to its off state when said second switching transistor is in its on state, and said signal source means is connected to the base of said second switching transistor for turning the latter to its on state upon the occurrence of said gating signal.

Claim 8

A transistor combination circuit comprising an input terminal receiving a composite stereophonic sound signal; a pair of transistor circuits each performing a gating operation and each including signal transmitting means for transmitting said signal from said input terminal to a respective output terminal and signal shunting means connected to said transmitting means between said input terminal and said respective output terminal and having switching transistor means operative to form a shunt path for gating the signal in the respective transmitting means; signal source means for applying a gating signal to said shunting means of each of said transistor circuits and thereby causing said pair of transistor circuits to alternately perform a gating operation in response to said gating signal with separated right and left sound signals being obtained at the respective output terminals of the transmitting means of said pair of transistor circuits, and means for applying a bias voltage to said switching transistor means of each of said transistor circuits so as to cause each of said switching transistor means to be in an inactive state except when made operative in response to said gating signal.

Claim 9

A transistor combination circuit comprising an input terminal receiving a composite stereophonic sound signal; a pair of transistor circuits each performing a gating operation and each including signal transmitting means for transmitting said signal from said input terminal to a respective output terminal and signal shunting means connected to said transmitting means between said input terminal and said respective output terminal and having switching transistor means operative to form a shunt path for gating the signal in the respective transmitting means; signal source means for applying a gating signal to said shunting means of each of said transistor circuits and thereby causing said pair of transistor circuits to alternately perform a gating operation in response to said gating signal with separated right and left sound signals being obtained at the respective output terminals of the transmitting means of said pair of transistor circuits, and means for applying a bias voltage to said switching transistor means of each of said transistor circuits so as to cause each of said switching transistor means to be in an inactive state except when made operative in response to said gating signal.

Claim 10

A transistor combination circuit according to claim 8 in which said switching transistor means of each of said transistor circuits includes at least a first transistor having a collector and emitter between which the respective shunt path is formed when said first transistor is in its on state, and said means for applying a bias voltage applies substantially the same voltage to said collector and emitter of said first transistor.

Claim 11

A transistor combination circuit according to claim 7, further comprising switching circuit means for muting the signals in said transmitting means in response to a muting signal supplied thereto.

Claim 12

A transistor combination circuit according to claim 9, in which said switching circuit means is connected in common to both of said pair of transistor circuits performing the gating operation.