US3704382A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bistable throttle control system
Assignee: Motors Liquidation Co
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Filing: 1971-07-02
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Granted: 1972-11-28
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Expires: 1991-07-02
Abstract
Abstract A throttle valve the complete closure of which is prevented by a throttle stop that is advanced be electrically activated vacuum means above a preset speed of an engine responsive to the setting of the throttle valve and retracted below this speed. Pulse generating means connected with the engine provide an input to a timing stage that is operatively connected by capacitor, Zener diode, and amplifier means to means that advance and retract the throttle stop when the speed of the engine is respectively above and below the preset speed.
Inventors
- 👤 Gerald O Huntzinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:51
CPC Classifications
F; F02; F02D; F02D31/00; F02D31/001; F02D31/002
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
255 words
A bi-stable frequency sensitive circuit receiving an input signal thereto and providing a response therefrom, said circuit connected with a voltage source and comprising: a. signal generating and shaping means for developing a pulsating signal proportional to said input signal; b. first timing means having an input connected with said signal generating and shaping means and operative in response to said pulsating signal for producing at an output a first output when the frequency of said pulsating signal is above a predetermined frequency and a second output when the frequency of said pulsating signal is below said predetermined frequency; c. second timing means comprising a transistor connected with said output of said first timing means to receive said first and second output signals therefrom, a resistor connected with said transistor and said source, and a capacitor connected with said resistor, whereby said capacitor is charged to a predetermined voltage through said resistor when the output of said first timing means is one of said first and second output signals and is discharged through said transistor before attaining said predetermined voltage when the output of said first timing means is the other of said first and second output signals; d. a constant impedance breakdown device connected with said capacitor and operative to break down when said capacitor is charged to said predetermined voltage; and, e. utilization means connected with said constant impedance breakdown device and operable to produce a response when the output of said first Timing means is one of said first and second outputs.
Claim 2
Dependent Claim
255 words
A bi-stable frequency sensitive circuit receiving an input signal thereto and providing a response therefrom, said circuit connected with a voltage source and comprising: a. signal generating and shaping means for developing a pulsating signal proportional to said input signal; b. first timing means having an input connected with said signal generating and shaping means and operative in response to said pulsating signal for producing at an output a first output when the frequency of said pulsating signal is above a predetermined frequency and a second output when the frequency of said pulsating signal is below said predetermined frequency; c. second timing means comprising a transistor connected with said output of said first timing means to receive said first and second output signals therefrom, a resistor connected with said transistor and said source, and a capacitor connected with said resistor, whereby said capacitor is charged to a predetermined voltage through said resistor when the output of said first timing means is one of said first and second output signals and is discharged through said transistor before attaining said predetermined voltage when the output of said first timing means is the other of said first and second output signals; d. a constant impedance breakdown device connected with said capacitor and operative to break down when said capacitor is charged to said predetermined voltage; and, e. utilization means connected with said constant impedance breakdown device and operable to produce a response when the output of said first Timing means is one of said first and second outputs.
Claim 3
Dependent Claim
288 words
A bi-stable frequency sensitive circuit receiving an input signal thereto and providing a response therefrom, said circuit connected with a voltage source and comprising: a. a source of constant potential; b. signal generating and shaping means for developing a pulsating signal proportional to said input signal; c. first timing means comprising a first transistor connected with said signal generating and shaping means, a resistor connected with said source and said first transistor, a capacitor connected with said first transistor and said resistor, and a unijunction transistor connected with said capacitor, whereby said unijunction transistor produces a first output when the frequency of said input signal is above a predetermined frequency and a second output when the frequency of said input signal is below said predetermined frequency; d. second timing means comprising a second transistor connected with said unijunction transistor to receive said first and second output signals therefrom, a second resistor connected with said second transistor and said source, and a second capacitor connected with said second resistor, whereby said second capacitor is charged to a predetermined voltage through said second resistor when the output from said first timing means is one of said first and second output signals and is discharged through said second transistor before attaining said predetermined voltage when the output of said first timing means is the other of said first and second output signals; e. a constant impedance breakdown device connected with said second capacitor and operative to break down when said second capacitor is charged to said predetermined voltage; and f. amplifier means connected with said constant impedance breakdown device and operable to produce a response when the output of said first timing means is one of said first and second outputs.
Claim 4
Dependent Claim
288 words
A bi-stable frequency sensitive circuit receiving an input signal thereto and providing a response therefrom, said circuit connected with a voltage source and comprising: a. a source of constant potential; b. signal generating and shaping means for developing a pulsating signal proportional to said input signal; c. first timing means comprising a first transistor connected with said signal generating and shaping means, a resistor connected with said source and said first transistor, a capacitor connected with said first transistor and said resistor, and a unijunction transistor connected with said capacitor, whereby said unijunction transistor produces a first output when the frequency of said input signal is above a predetermined frequency and a second output when the frequency of said input signal is below said predetermined frequency; d. second timing means comprising a second transistor connected with said unijunction transistor to receive said first and second output signals therefrom, a second resistor connected with said second transistor and said source, and a second capacitor connected with said second resistor, whereby said second capacitor is charged to a predetermined voltage through said second resistor when the output from said first timing means is one of said first and second output signals and is discharged through said second transistor before attaining said predetermined voltage when the output of said first timing means is the other of said first and second output signals; e. a constant impedance breakdown device connected with said second capacitor and operative to break down when said second capacitor is charged to said predetermined voltage; and f. amplifier means connected with said constant impedance breakdown device and operable to produce a response when the output of said first timing means is one of said first and second outputs.
References Cited (Backward Citations)
US3517218A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-11-28 | 1976-05-29 | 1976-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-11-28 | 1980-05-29 | 1980-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-11-28 | 1984-05-29 | 1984-11-28 | $7700.00 | Window Closed / Lapsed |