Memory cell with voltage limiting at transistor control terminals

Claim 2

A memory cell having first and second junction transistors with base-collector cross-coupling and with common emitters coupled through an emitter resistor to a fixed voltage source, a pair of collector resistors respectively coupling the transistor collectors to a word line, and an output transistor having its base coupled to the first transistor collector and its emitter coupled to a sense line, the improvement comprising: voltage responsive voltage limiting means coupled to said first transistor base terminal for restricting the voltage level established thereat to a predetermined maximum value so as to selectively effect positive control of the state of conductIon of said first transistor; and level setting means coupled to said sense line for selectively establishing a predetermined voltage level thereon, said level setting means being adapted to cause conduction of said first transistor and non-conduction of said second transistor.

Claim 3

A memory cell having first and second junction transistors with base-collector cross-coupling and with common emitters coupled through an emitter resistor to a fixed voltage source, a pair of collector resistors respectively coupling the transistor collectors to a word line, and an output transistor having its base coupled to the first transistor collector and its emitter coupled to a sense line, the improvement comprising: voltage responsive voltage limiting means coupled to said first transistor base terminal for restricting the voltage level established thereat to a predetermined maximum value so as to selectively effect positive control of the state of conductIon of said first transistor; and level setting means coupled to said sense line for selectively establishing a predetermined voltage level thereon, said level setting means being adapted to cause conduction of said first transistor and non-conduction of said second transistor.

Claim 4

A memory cell having first and second junction transistors with base-collector cross-coupling and with common emitters coupled through an emitter resistor to a fixed voltage source, a pair of collector resistors respectively coupling the transistor collectors to a word line, and an output transistor having its base coupled to the first transistor collector and its emitter coupled to a sense line, the improvement comprising: voltage responsive voltage limiting means coupled to said first transistor base terminal for restricting the voltage level established thereat to a predetermined maximum value so as to selectively effect positive control of the state of conductIon of said first transistor; and level setting means coupled to said sense line for selectively establishing a predetermined voltage level thereon, said level setting means being adapted to cause conduction of said first transistor and non-conduction of said second transistor.

Claim 5

An information storage element comprising: first and second switch elements each having a control terminal and two primary current conduction terminals; means intercoupling said first and second switch elements for controlling conduction of said elements in order to provide complementary conducting states at said primary conduction terminals; first voltage responsive voltage limiting means coupled to said control terminal of said first switch element to restrict the maximum voltage level established thereat to a predetermined value so as to selectively control conduction thereof responsive to operation of said first voltage limiting means; and control means to selectively establish a first voltage level and a second voltage level respectively in excess of said predetermined value and less than said predetermined value; said control means being coupled to the control terminals of said first and second switch elements so as to selectively control conduction of said switch elements in order to effect operation thereof in a first predetermined complementary conducting state responsive to the establishment of said first voltage level.

Claim 6

An information storage element comprising: first and second switch elements each having a control terminal and two primary current conduction terminals; means intercoupling said first and second switch elements for controlling conduction of said elements in order to provide complementary conducting states at said primary conduction terminals; first voltage responsive voltage limiting means coupled to said control terminal of said first switch element to restrict the maximum voltage level established thereat to a predetermined value so as to selectively control conduction thereof responsive to operation of said first voltage limiting means; and control means to selectively establish a first voltage level and a second voltage level respectively in excess of said predetermined value and less than said predetermined value; said control means being coupled to the control terminals of said first and second switch elements so as to selectively control conduction of said switch elements in order to effect operation thereof in a first predetermined complementary conducting state responsive to the establishment of said first voltage level.

Claim 7

The storage element of claim 2 additionally comprising; second voltage limiting means coupled to said control terminal of said second switch element and adapted to be selectively activated responsive to the establishment of said first voltage to restrict the maximum voltage applied to said second control terminal to a value less than said predetermined value so as to effect operation of said switch elements in a second predetermined complementary conducting state.

Claim 8

The storage element of claim 3 wherein said control means includes a third switch element coupled to said control element of said second switch element, said third switch element being adapted to selectively establish the second voltage level.

Claim 9

The storage element of claim 2 wherein said first voltage responsive voltage limiting means comprises at least one unidirectional semiconductor device.

Claim 10

The storage element of claim 5 wherein said at least one unidirectional semiconductor device comprises a plurality of serially connected diodes for maintaining said first switch element in a predetermined state responsive to operation of said diodes.