US3703679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current regulator with delayed turn-off
Assignee: Collins Radio Co
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Filing: 1971-10-28
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Granted: 1972-11-21
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Expires: 1991-10-28
Abstract
Abstract A voltage regulator with delayed current turn-off characteristics particularly useful with capacitive loads and including a load current control transistor, control circuitry for the current control transistor, and load current sensing circuitry the control circuitry being responsive to excess load current and biasing the load current control transistor to limit current. Transistor circuitry is provided within the control circuitry whereby continued excess current for a predetermined period of time will remove the power supply by interrupting the current to the load.
Inventors
- 👤 Marvin W Heidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:58
CPC Classifications
H; H02; H02J; H02J3/00; H02J3/18; H02J3/1892; G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/565; G05F1/569; G05F1/573; H02J3/1821; H02J3/1828; Y; Y02; Y02E; Y02E40/00; Y02E40/30
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
203 words
A current regulator with delayed cut-off characteristics comprising transistor current control means for serially connecting with a load, first means for forward biasing said current control means for normal load currents, second means for reducing said forward bias when load current exceeds a preselected value, said second means including a first transistor connected between said current control means and a first reference voltage means, second reference voltage means serially connected through resistive means to the base terminal of said first transistor, second and third transistors, said second transistor connected between said base terminal of said first transistor and a voltage charging circuit, said third transistor connected between the control terminal of said second transistor and a regulator input terminal, current sensing means for serially connecting with said load, means connecting said current sensing means to the control terminal of said third transistor whereby an excess current renders said third transistor conductive, the conductivity of said third transistor rendering said second transistor conductive and charging said voltage charging means, and means connecting said voltage charging means and the control terminal of said third transistor whereby said third transistor is driven into saturation when accumulated charge on said voltage charging means provides saturation bias thereto.
Claim 2
Dependent Claim
203 words
A current regulator with delayed cut-off characteristics comprising transistor current control means for serially connecting with a load, first means for forward biasing said current control means for normal load currents, second means for reducing said forward bias when load current exceeds a preselected value, said second means including a first transistor connected between said current control means and a first reference voltage means, second reference voltage means serially connected through resistive means to the base terminal of said first transistor, second and third transistors, said second transistor connected between said base terminal of said first transistor and a voltage charging circuit, said third transistor connected between the control terminal of said second transistor and a regulator input terminal, current sensing means for serially connecting with said load, means connecting said current sensing means to the control terminal of said third transistor whereby an excess current renders said third transistor conductive, the conductivity of said third transistor rendering said second transistor conductive and charging said voltage charging means, and means connecting said voltage charging means and the control terminal of said third transistor whereby said third transistor is driven into saturation when accumulated charge on said voltage charging means provides saturation bias thereto.
Claim 3
Dependent Claim
203 words
A current regulator with delayed cut-off characteristics comprising transistor current control means for serially connecting with a load, first means for forward biasing said current control means for normal load currents, second means for reducing said forward bias when load current exceeds a preselected value, said second means including a first transistor connected between said current control means and a first reference voltage means, second reference voltage means serially connected through resistive means to the base terminal of said first transistor, second and third transistors, said second transistor connected between said base terminal of said first transistor and a voltage charging circuit, said third transistor connected between the control terminal of said second transistor and a regulator input terminal, current sensing means for serially connecting with said load, means connecting said current sensing means to the control terminal of said third transistor whereby an excess current renders said third transistor conductive, the conductivity of said third transistor rendering said second transistor conductive and charging said voltage charging means, and means connecting said voltage charging means and the control terminal of said third transistor whereby said third transistor is driven into saturation when accumulated charge on said voltage charging means provides saturation bias thereto.
Claim 4
Dependent Claim
203 words
A current regulator with delayed cut-off characteristics comprising transistor current control means for serially connecting with a load, first means for forward biasing said current control means for normal load currents, second means for reducing said forward bias when load current exceeds a preselected value, said second means including a first transistor connected between said current control means and a first reference voltage means, second reference voltage means serially connected through resistive means to the base terminal of said first transistor, second and third transistors, said second transistor connected between said base terminal of said first transistor and a voltage charging circuit, said third transistor connected between the control terminal of said second transistor and a regulator input terminal, current sensing means for serially connecting with said load, means connecting said current sensing means to the control terminal of said third transistor whereby an excess current renders said third transistor conductive, the conductivity of said third transistor rendering said second transistor conductive and charging said voltage charging means, and means connecting said voltage charging means and the control terminal of said third transistor whereby said third transistor is driven into saturation when accumulated charge on said voltage charging means provides saturation bias thereto.
Claim 5
Dependent Claim
33 words
A current regulator as defined by claim 1 wherein said first means for forward biasing comprises resistive means connecting the control terminal of said transistor current control means with a regulator input terminal.
Claim 6
Dependent Claim
47 words
A current regulator as defined by claim 1 wherein said first reference voltage means comprises a voltage divider connected across the output terminal of said regulator and said second reference voltage means comprises zener diode means connected between a regulator input terminal and a regulator output terminal.
Claim 7
Dependent Claim
25 words
A current regulator as defined by claim 1 wherein said voltage charging circuit comprises a charging capacitor and a charge dissipating resistor connected in parallel.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-11-21 | 1976-05-22 | 1976-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-11-21 | 1980-05-22 | 1980-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-11-21 | 1984-05-22 | 1984-11-21 | $7700.00 | Window Closed / Lapsed |