Parity checked shift register counters

Claim 2

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of four individual shift register stages S0 to S3 adaptable for counting to a number J selectable from 22 to 23 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage, S3, a first logic circuit means interposed between stage S2 and stage S1 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a four input AND gate, the outputs of stage S2 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S1, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the four counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 3

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of five individual shift register stages S0 to S4 adaptable for counting to a number J selectable from 23 to 24 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage, S4, a first logic circuit means interposed between stage S3 and stage S2 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a five input AND gate, the outputs of stage S3 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S2, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the five counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 4

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of five individual shift register stages S0 to S4 adaptable for counting to a number J selectable from 23 to 24 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage, S4, a first logic circuit means interposed between stage S3 and stage S2 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a five input AND gate, the outputs of stage S3 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S2, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the five counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 5

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of six individual shift register stages S0 to S5 adaptable for counting to a number J selectable from 24 to 25 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S5, a first logic circuit means interposed between stage S5 and stage S4 and a second logic circuit means interposed between stage S4 and stage S3, both said logic circuit means including in each case two, two input exclusive-OR circuits and a six input AND gate, the outputs of stage S5 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S4, the outputs of stage S4 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S3, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the six counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 6

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of six individual shift register stages S0 to S5 adaptable for counting to a number J selectable from 24 to 25 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S5, a first logic circuit means interposed between stage S5 and stage S4 and a second logic circuit means interposed between stage S4 and stage S3, both said logic circuit means including in each case two, two input exclusive-OR circuits and a six input AND gate, the outputs of stage S5 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S4, the outputs of stage S4 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S3, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the six counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 7

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of seven individual shift register stages S0 to S6 adaptable for counting to a number J selectable from 25 to 26 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S6, a first logic circuit means interposed between stage S5 and stage S4 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a seven input AND gate, the outputs of stage S5 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S4, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the seven counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 8

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of seven individual shift register stages S0 to S6 adaptable for counting to a number J selectable from 25 to 26 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S6, a first logic circuit means interposed between stage S5 and stage S4 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a seven input AND gate, the outputs of stage S5 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S4, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the seven counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 9

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of eight individual shift register stages S0 to S6 adaptable for counting to a number J selectable from 26 to 27 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S7, a first logic circuit means interposed between stage S4 and stage S3 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and an eight input AND gate, the outputs of stage S4 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S3, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, add the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the eight counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 10

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of eight individual shift register stages S0 to S6 adaptable for counting to a number J selectable from 26 to 27 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S7, a first logic circuit means interposed between stage S4 and stage S3 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and an eight input AND gate, the outputs of stage S4 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S3, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, add the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the eight counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 11

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of nine individual shift register stages S0 to S8 adaptable for counting to a number J selectable from 27 to 28 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S8, a first logic circuit means interposed between stage S6 and stage S5 and a second logic circuit means interposed between stage S4 and stage S3, both said logic circuit means including in each case two, two input exclusive-OR circuits and a nine input AND gate, the outputs of stage S6 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit aNd the output of the second exclusive-OR circuit providing the input to stage S5, the outputs of stage S4 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S3, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the nine counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 12

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of nine individual shift register stages S0 to S8 adaptable for counting to a number J selectable from 27 to 28 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S8, a first logic circuit means interposed between stage S6 and stage S5 and a second logic circuit means interposed between stage S4 and stage S3, both said logic circuit means including in each case two, two input exclusive-OR circuits and a nine input AND gate, the outputs of stage S6 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit aNd the output of the second exclusive-OR circuit providing the input to stage S5, the outputs of stage S4 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S3, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the nine counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 13

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 10 individual shift register stages S0 to S9 adaptable for counting to a number J selectable from 28 to 29 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage S0, provides an input to the highest-order stage S9, a first logic circuit means interposed between stage S8 and stage S7 and a second logic circuit means interposed between stage S5 and stage S4, both said logic circuit means including in each case two, two input exclusive-OR circuits and a ten input AND gate, the outputs of stage S8 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S7, the outputs of stage S5 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S4, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 10 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 14

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 10 individual shift register stages S0 to S9 adaptable for counting to a number J selectable from 28 to 29 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage S0, provides an input to the highest-order stage S9, a first logic circuit means interposed between stage S8 and stage S7 and a second logic circuit means interposed between stage S5 and stage S4, both said logic circuit means including in each case two, two input exclusive-OR circuits and a ten input AND gate, the outputs of stage S8 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S7, the outputs of stage S5 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S4, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 10 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 15

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 11 individual shift register stages S0 to S10 adaptable for counting to a number J selectable from 29 to 210 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S10, a first logic circuit means interposed between stage S10 and stage S9 and a second logic circuit means interposed between stage S8 and stage S7, both said logic circuit means including in each case two, two input exclusive-OR circuits and an 11 input AND gate, the outputs of stage S10 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S9, the outputs of stage S8 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit meAns and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S7, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 11 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 16

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 11 individual shift register stages S0 to S10 adaptable for counting to a number J selectable from 29 to 210 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S10, a first logic circuit means interposed between stage S10 and stage S9 and a second logic circuit means interposed between stage S8 and stage S7, both said logic circuit means including in each case two, two input exclusive-OR circuits and an 11 input AND gate, the outputs of stage S10 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S9, the outputs of stage S8 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit meAns and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S7, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 11 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 17

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 12 individual shift register stages S0 to S11 adaptable for counting to a number J selectable from 210 to 211 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S11, a first logic circuit means interposed between stage S7 and stage S6 and a second logic circuit means interposed between stage S2 and stage S1, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 12 input AND gate, the outputs of stage S7 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S6, the outputs of stage S2 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S1, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 12 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 18

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 12 individual shift register stages S0 to S11 adaptable for counting to a number J selectable from 210 to 211 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S11, a first logic circuit means interposed between stage S7 and stage S6 and a second logic circuit means interposed between stage S2 and stage S1, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 12 input AND gate, the outputs of stage S7 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S6, the outputs of stage S2 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S1, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 12 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 19

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 13 individual shift register stages S0 to S12 adaptable for counting to a number J selectable from 211 to 212 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S12, a first logic circuit means interposed between stage S11 and stage S10 and a second logic circuit means interposed between stage S10 and stage S9, both said logic circuit means including in each case two, two input exclusive-OR circuit and a 13 input AND gate, a fifth exclusive-OR circuit connected directly between stage S7 and stage S6 and a sixth exclusive-OR circuit connected directly between stage S6 and stage S5, the outputs of stage S11 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S10, the outputs of stage S10 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first eXclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S9, the outputs of stage S7 and the lowest-order stage S0 providing the two inputs to the fifth exclusive-OR, and the output of the fifth exclusive-OR providing the input to stage S6, the outputs of stage S6 and the lowest-order stage S0 providing the two inputs to the sixth exclusive-OR and the output of the sixth exclusive-OR providing the input to stage S5, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 13 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 20

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 13 individual shift register stages S0 to S12 adaptable for counting to a number J selectable from 211 to 212 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S12, a first logic circuit means interposed between stage S11 and stage S10 and a second logic circuit means interposed between stage S10 and stage S9, both said logic circuit means including in each case two, two input exclusive-OR circuit and a 13 input AND gate, a fifth exclusive-OR circuit connected directly between stage S7 and stage S6 and a sixth exclusive-OR circuit connected directly between stage S6 and stage S5, the outputs of stage S11 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S10, the outputs of stage S10 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first eXclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S9, the outputs of stage S7 and the lowest-order stage S0 providing the two inputs to the fifth exclusive-OR, and the output of the fifth exclusive-OR providing the input to stage S6, the outputs of stage S6 and the lowest-order stage S0 providing the two inputs to the sixth exclusive-OR and the output of the sixth exclusive-OR providing the input to stage S5, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 13 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 21

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 14 individual shift register stages S0 to S13 adaptable for counting to a number J selectable from 212 to 213 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S13, a first logic circuit means interposed between stage S2 and stage S1 and a second logic circuit means interposed between stage S1 and stage S0 , both said logic circuit means including in each case two, two input exclusive-OR circuits and a 14 input AND gate, the outputs of stage S2 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S1, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 14 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 22

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 14 individual shift register stages S0 to S13 adaptable for counting to a number J selectable from 212 to 213 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S13, a first logic circuit means interposed between stage S2 and stage S1 and a second logic circuit means interposed between stage S1 and stage S0 , both said logic circuit means including in each case two, two input exclusive-OR circuits and a 14 input AND gate, the outputs of stage S2 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S1, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 14 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 23

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 15 individual shift register stages S0 to S14 adaptable for counting to a number J selectable from 213 to 214 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S14, a first logic circuit means interposed between stage S12 and stage S11 and a second logic circuit means interposed between stage S10 and stage S9, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 15 input AND gate, the outputs of stage S12 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S11, the outputs of stage S10 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S9, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 15 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 24

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 15 individual shift register stages S0 to S14 adaptable for counting to a number J selectable from 213 to 214 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S14, a first logic circuit means interposed between stage S12 and stage S11 and a second logic circuit means interposed between stage S10 and stage S9, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 15 input AND gate, the outputs of stage S12 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S11, the outputs of stage S10 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S9, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 15 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 25

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 16 individual shift register stages S0 to S15 adaptable for counting to a number J selectable from 214 to 215 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S15, a first logic circuit means interposed between stage S14 and stage S13 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 16 input AND gate, the outputs of stage S14 and the lowest-order stage providing the two inputs to the first exclusive-oR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S13, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 16 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 26

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 16 individual shift register stages S0 to S15 adaptable for counting to a number J selectable from 214 to 215 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S15, a first logic circuit means interposed between stage S14 and stage S13 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 16 input AND gate, the outputs of stage S14 and the lowest-order stage providing the two inputs to the first exclusive-oR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S13, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 16 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 27

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 17 individual shift register stages S0 to S16 adaptable for counting to a number J selectable from 215 to 216 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage, S16, a first logic circuit means interposed between stage S11 and stage S10 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and 17 input AND gate, the outputs of stage S11 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S10, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output oF the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0 , the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 17 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 28

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 17 individual shift register stages S0 to S16 adaptable for counting to a number J selectable from 215 to 216 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage, S16, a first logic circuit means interposed between stage S11 and stage S10 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and 17 input AND gate, the outputs of stage S11 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic-circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S10, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output oF the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0 , the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 17 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 29

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 18 individual shift register stages S0 to S17 adaptable for counting to a number J selectable from 216 to 217 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage, S17 a first logic circuit means interposed between stage S14 and stage S13 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and an 18 input AND gate, the outputs of stage S14 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S13, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 18 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 30

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 18 individual shift register stages S0 to S17 adaptable for counting to a number J selectable from 216 to 217 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage, S17 a first logic circuit means interposed between stage S14 and stage S13 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and an 18 input AND gate, the outputs of stage S14 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S13, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 18 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 31

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 19 individual shift register stages S0 to S18 adaptable for counting to a number J selectable from 217 to 218 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S18, a first logic circuit means interposed between stage S13 and stage S12 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 19 input AND gate, the outputs of stage S13 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S12, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logIc circuit means being identical and being obtained from each of the 19 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 32

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 19 individual shift register stages S0 to S18 adaptable for counting to a number J selectable from 217 to 218 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S18, a first logic circuit means interposed between stage S13 and stage S12 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 19 input AND gate, the outputs of stage S13 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S12, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logIc circuit means being identical and being obtained from each of the 19 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 33

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 20 individual shift register stages S0 to S19 adaptable for counting to a number J selectable from 218 to 219 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S19, a first logic circuit means interposed between stage S14 and stage S13 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 20 input AND gate, the outputs of stage S14 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S13, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 19 counter stages, each input from each stage being selected from the true and complement output of that stage.

Claim 34

A self-testing fixed parity shift register counter having no fixed parity bit, said counter being comprised of 20 individual shift register stages S0 to S19 adaptable for counting to a number J selectable from 218 to 219 -2, said stages being interconnected so that the output of any given stage Si becomes the input of the adjacent lower-order stage (Si 1) and wherein the output of a lowest-order stage, S0, provides an input to the highest-order stage S19, a first logic circuit means interposed between stage S14 and stage S13 and a second logic circuit means interposed between stage S1 and stage S0, both said logic circuit means including in each case two, two input exclusive-OR circuits and a 20 input AND gate, the outputs of stage S14 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the first logic circuit means and the output of the first exclusive-OR circuit and the output of said AND gate providing the input to the second exclusive-OR circuit and the output of the second exclusive-OR circuit providing the input to stage S13, the outputs of stage S1 and the lowest-order stage providing the two inputs to the first exclusive-OR circuit of the second logic circuit means and the output of the first exclusive-OR circuit and the output of the AND circuit providing the input to the second exclusive-OR circuit, and the output of the second exclusive-OR circuit providing the input to stage S0, the inputs to the two AND circuits in said two logic circuit means being identical and being obtained from each of the 19 counter stages, each input from each stage being selected from the true and complement output of that stage.