US3701857A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multifrequency signal receiving circuit
Assignee: Fujitsu Ltd
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Filing: 1971-06-28
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Granted: 1972-10-31
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Expires: 1991-06-28
Abstract
Abstract A plurality of bandpass filters equal in number to the number of frequencies of multifrequency input signals supplied thereto select the input signals. Each of a plurality of signal detectors is connected to a corresponding one of the bandpass filters and provides pulse trains corresponding to the frequencies of the signals selected by the bandpass filters. A plurality of OR gates is provided. Each of the OR gates has a first input connected to the output of a corresponding one of the signal detectors, a second input and an output. An additional OR gate has a plurality of inputs each connected to the output of a corresponding one of the signal detectors and an output for providing an output pulse train. A rectifier circuit has an input connected to the output of the additional OR gate and converts the output pulse train of the additional OR gate into continuous signals. A plurality of AND gates is provided. Each of the AND gates has a first input connected to the output of a corresponding one of the plurality of OR gates, a second input connected to the output of the rectifier circuit and an output connected to the second input of a corresponding one of the plurality of OR gates. The outputs are derived from the outputs of the AND gates.
Inventors
- 👤 Shogo Usuda
- 👤 Susumu Mizusawa
- 👤 Harunobu Tateno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:22
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/453
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
240 words
A multifrequency signal receiving circuit, comprising input means for providing multifrequency input signals; a plurality of bandpass filters equal in number to the number of frequencies of the multifrequency input signals connected in common to the input means for selecting the input signals; a plurality of signal detectors each having an input connected to a corresponding one of the bandpass filters and an output for providing pulse trains corresponding to the frequencies of the signals selected by the bandpass filters; a plurality of OR gates each having a first input connected to the output of a corresponding one of the signal detectors, a second input and an output; an additional OR gate having a plurality of inputs each connected to the output of a corresponding one of the signal detectors and an output for providing an output pulse train; a rectifier circuit having an input connected to the output of the additional OR gate and an output for converting the output pulse train of the additional OR gate into continuous signals; a plurality of AND gates each having a first input connected to the output of a corresponding one of the plurality of OR gates, a second input connected to the output of the rectifier circuit and an output connected to the second input of a corresponding one of the plurality of OR gates; and output means connected to the outputs of the AND gates for providing continuous output signals.
Claim 2
Dependent Claim
240 words
A multifrequency signal receiving circuit, comprising input means for providing multifrequency input signals; a plurality of bandpass filters equal in number to the number of frequencies of the multifrequency input signals connected in common to the input means for selecting the input signals; a plurality of signal detectors each having an input connected to a corresponding one of the bandpass filters and an output for providing pulse trains corresponding to the frequencies of the signals selected by the bandpass filters; a plurality of OR gates each having a first input connected to the output of a corresponding one of the signal detectors, a second input and an output; an additional OR gate having a plurality of inputs each connected to the output of a corresponding one of the signal detectors and an output for providing an output pulse train; a rectifier circuit having an input connected to the output of the additional OR gate and an output for converting the output pulse train of the additional OR gate into continuous signals; a plurality of AND gates each having a first input connected to the output of a corresponding one of the plurality of OR gates, a second input connected to the output of the rectifier circuit and an output connected to the second input of a corresponding one of the plurality of OR gates; and output means connected to the outputs of the AND gates for providing continuous output signals.
Claim 3
Dependent Claim
117 words
A multifrequency signal receiving circuit as claimed in claim 1, wherein the rectifier circuit comprises an Input terminal connected to the output of the additional OR gate, a capacitor connected to the input terminal, a resistor, a diode connected in parallel with the resistor, the parallel-connected resistor and diode being connected in series between the capacitor and a point at ground potential, an inverter circuit connected to a common point in the connection between the capacitor and the parallel-connected resistor and diode, a NAND gate having a first input connected to the input terminal, a second input connected to the inverter circuit and an output, and an output terminal connected to the output of the NAND gate.
Claim 4
Dependent Claim
111 words
A multifrequency signal receiving circuit as claimed in claim 1, wherein the rectifier circuit comprises an input terminal connected to the output of the additional OR gate, a capacitor connected to the input terminal, a resistor connected in series circuit arrangement with the capacitor, an inverter circuit connected to the series circuit arrangement, means for applying a positive potential to a common point point in the connection between the series circuit arrangement and the inverter circuit, an OR gate having a first input connected to the input terminal, a second input connected to the inverter circuit and an output, and an output terminal connected to the output of the OR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-31 | 1976-05-01 | 1976-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-31 | 1980-05-01 | 1980-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-31 | 1984-05-01 | 1984-10-31 | $7700.00 | Window Closed / Lapsed |