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US3701144A Expired / Lapsed US ⏱️ 0.0 years remaining

High frequency analog-to-digital converter

Assignee: United States Department of the Navy
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Filing: 1970-10-28
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Granted: 1972-10-24
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Expires: 1990-10-28
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Abstract

Abstract An analog-to-digital converter having a signal generator providing a sinusoidal reference signal which is to be compared to a high frequency analog signal, a plurality of threshold units each biased to trigger an output signal at a predetermined discrete level of the difference between the reference signal and the analog signal, a memory reset unit receiving the reference signal and providing a reset signal for clearing the output signals therefrom at a predetermined time in each cycle of the reference signal, and an encoder receiving the output signals of the threshold units and converting them into a digital code. The time of the reset signal is determined to be after either positive or negative peak of the reference signal.

Inventors

  • 👤 Dennis E Fineran
  • 👤 Samuel J Fendley

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 06:21
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/36; H03M1/361

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 274 words
A high frequency analog-to-digital converter for an analog signal comprising, in combination: signal generating means for producing a sinusoidal sampling reference signal at a frequency and amplitude always greater than the maximum anticipated frequency and amplitude of an analog signal to be converted; reset means connected to receive the reference signal for producing a reset pulse in each cycle thereof; and threshold means including a plurality of threshold units each unit having subtracting means adapted to receive the analog signaL and connected to receive the sinusoidal reference signal for providing output difference signals indicative of an amplitude difference between the analog and reference signals, and including first and second resistors having their one ends connected in common and their other ends receiving respectively the analog and sinusoidal reference signals, and wherein the resistances of said first and second resistors is selected to provide a greater peak current of the reference signal through said second resistor than the anticipated peak current of the analog signal through said first resistor, and sampling means connected to receive the difference signals and the reset pulse for producing parallel output signals indicative of a peak amplitude of respective ones of the difference signals between adjacent reset pulses, and including a third resistor having its one end connected in common to said first and second resistors and its other end to a d.c. signal, and a diode unit connected to an input to the one ends of said resistors and providing the threshold unit output signal, the duration between the reset pulses being preselected to include the time of the peak amplitude of all anticipated frequencies of the difference signals.
Claim 2
Dependent Claim 274 words
A high frequency analog-to-digital converter for an analog signal comprising, in combination: signal generating means for producing a sinusoidal sampling reference signal at a frequency and amplitude always greater than the maximum anticipated frequency and amplitude of an analog signal to be converted; reset means connected to receive the reference signal for producing a reset pulse in each cycle thereof; and threshold means including a plurality of threshold units each unit having subtracting means adapted to receive the analog signaL and connected to receive the sinusoidal reference signal for providing output difference signals indicative of an amplitude difference between the analog and reference signals, and including first and second resistors having their one ends connected in common and their other ends receiving respectively the analog and sinusoidal reference signals, and wherein the resistances of said first and second resistors is selected to provide a greater peak current of the reference signal through said second resistor than the anticipated peak current of the analog signal through said first resistor, and sampling means connected to receive the difference signals and the reset pulse for producing parallel output signals indicative of a peak amplitude of respective ones of the difference signals between adjacent reset pulses, and including a third resistor having its one end connected in common to said first and second resistors and its other end to a d.c. signal, and a diode unit connected to an input to the one ends of said resistors and providing the threshold unit output signal, the duration between the reset pulses being preselected to include the time of the peak amplitude of all anticipated frequencies of the difference signals.
Claim 3
Dependent Claim 46 words
An analog-to-digital converter according to claim 1, wherein: the resistance of said third resistor in respective ones of said threshold units is selected to provide a discrete biasing current corresponding to increasing increments of the signal difference between the currents in said first and second resistors.
Claim 4
Dependent Claim 183 words
An analog-to-digital converter according to claim 2 further comprising: said diode unit in respective ones of said threshold units including a first tunnel diode connected at its anode to ground and connected at its cathode to the one ends of said first, second and third resistors for providing a switching signal when the current sum of said first, second and third resistor exceeds the switching current of said first tunnel diode, a blocking diode connected at its cathode to the cathode of said first tunnel diode and at its anode to one end of a loading resistor, a second tunnel diode connected at its cathode to the other end of said loading resistor and at its anode to ground for storing the switching of said first tunnel diode, and a reset resistor connected at one end to the cathode of said second tunnel diode and the other end receiving the reset pulses for clearing the signal stored in said second tunnel diode and for producing the output signal at the cathode of said second tunnel diode of respective ones of said threshold units.
Claim 5
Dependent Claim 27 words
A high frequency analog-to-digital converter according to claim 3 further comprising, in combination: encoder means receiving the parallel output signals for producing a digitally encoded signal thereof.

References Cited (Backward Citations)

US3237113A Cited
US3142056A Cited
US3305854A Cited
US3422226A Cited
US3396381A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-10-24 1976-04-24 1976-10-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-10-24 1980-04-24 1980-10-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-10-24 1984-04-24 1984-10-24 $7700.00 Window Closed / Lapsed

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