Patent US5716377A successfully refreshed from Google Patents.
US3701112A
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Balanced, incomplete, block designs for circuit links interconnecting switching network stages
Assignee: AT&T Inc
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Filing: 1971-06-04
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Granted: 1972-10-24
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Expires: 1991-06-04
Abstract
Abstract A first stage of a switching network includes a plurality v of switching matrices each including a predetermined number r of input signal terminals and output signal terminals. At least one different pair of links for signal path connection is provided for outputs of each pair of first stage matrices to some one of b k-input switching matrices of a second stage of the network. Links from any first stage matrix extend to only a portion of the output stage matrices and are arranged in accordance with a balanced, incomplete block design derived from combinatorial theory to distribute the link connections substantially evenly among the second stage matrices. The 2-stage network is itself a block design switching matrix that is useful for building higher order networks. A block design matrix also is combined, through time slot interchanging circuits or another switching stage, with a network of mirror image configuration so that signal path pairs established in the second network are the mirror image of path pairs established for the same communication through the first network.
Inventors
- 👤 David William Hagelbarger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:00
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
87 words
In combination, a first stage of plural switching arrays each including output terminals, a second stage of plural switching arrays each including input terminals, and means interconnecting each first stage switching array to only a portion of said second stage arrays, said interconnecting means including connecting links each extending between a different output terminal of said first stage and a discrete input terminal of said second stage, pairs of said links converging from any two different ones of said first stage arrays to a second stage array.
Claim 2
Dependent Claim
87 words
In combination, a first stage of plural switching arrays each including output terminals, a second stage of plural switching arrays each including input terminals, and means interconnecting each first stage switching array to only a portion of said second stage arrays, said interconnecting means including connecting links each extending between a different output terminal of said first stage and a discrete input terminal of said second stage, pairs of said links converging from any two different ones of said first stage arrays to a second stage array.
Claim 3
Dependent Claim
146 words
The combination in accordance with claim 1 in which said first stage arrays and said second stage arrays are arranged is ordered numerical sequences in their respective stages, said interconnecting means includes lambda selectable pairs of links each connecting a different one of said second stage arrays with a common pair of said first stage arrays, v arrays are provided in said first stage, and each of said first stage arrays has k output terminals and each of said second stage arrays has k input terminals, v and k being selected in relation to lambda in accordance with a symmetrical, balanced, incomplete, block design so that a block identifying the number of arrays in said second stage ordered numerical sequence to which output terminals of one of said first stage arrays are connected defines the format of blocks for all other arrays of said first stage.
Claim 4
Dependent Claim
146 words
In combination, a first stage of plural switching arrays each including output terminals, said arrays being numbered in an ordered sequence, a second stage of plural switching arrays each said second stage array including input terminals, said second stage arrays being numbered in an ordered sequence, and means interconnecting output terminals of each first stage array to input terminals of only a portion of said second stage arrays, said interconnecting means comprising link connecting means from each first stage array to a different second stage array in said second stage sequence, and link connecting means from the same first stage array to plural additional second stage arrays, all second stage arrays linked to such first stage array being spaced in said second stage sequence to provide at least two different number spans, in said second stage sequence, between adjacent ones of such linked second stage arrays.
Claim 5
Dependent Claim
146 words
In combination, a first stage of plural switching arrays each including output terminals, said arrays being numbered in an ordered sequence, a second stage of plural switching arrays each said second stage array including input terminals, said second stage arrays being numbered in an ordered sequence, and means interconnecting output terminals of each first stage array to input terminals of only a portion of said second stage arrays, said interconnecting means comprising link connecting means from each first stage array to a different second stage array in said second stage sequence, and link connecting means from the same first stage array to plural additional second stage arrays, all second stage arrays linked to such first stage array being spaced in said second stage sequence to provide at least two different number spans, in said second stage sequence, between adjacent ones of such linked second stage arrays.
Claim 6
Independent Claim
295 words
A method for finding a pair of connection paths between any selected pair of switching arrays of a first switching network stage and a switching array of a second switching network stage, the pathfinding being controlled by a data processing machine including a memory and operable in accordance with a program of stored instructions, said stages being interconnected by circuit links arranged in accordance with a cyclic balanced, incomplete, block design, said arrays being assigned, in their respective stages, numbers in an ordered numerical sequence, the method comprising the steps of establishing in said memory a table defining, for the lowest numbered one of said first stage arrays, a list of connection path pair identifier worDs, according to said block design, through said links to said second stage for array pairs with each other first stage switching array, each identifier including identification of an output terminal on said lowest numbered one of said first stage arrays, identification of one of said second stage switching arrays, and identification of an output terminal on the other one of said first stage arrays in the same first stage pair of arrays, determining an identification of a selected first stage first switching array which is to be paired with a selected second switching array of the same stage, finding the difference between said first and second array identifier numbers, securing from said table the identifier word corresponding to the one of said other first stage arrays having a number equal to said difference, and adding a subtrahend of the difference determination to the second stage array identifier in said corresponding word for finding, as a sum, the identification of a connecting one of said second stage arrays which is to be employed for pairing the selected first stage arrays.
Claim 7
Independent Claim
295 words
A method for finding a pair of connection paths between any selected pair of switching arrays of a first switching network stage and a switching array of a second switching network stage, the pathfinding being controlled by a data processing machine including a memory and operable in accordance with a program of stored instructions, said stages being interconnected by circuit links arranged in accordance with a cyclic balanced, incomplete, block design, said arrays being assigned, in their respective stages, numbers in an ordered numerical sequence, the method comprising the steps of establishing in said memory a table defining, for the lowest numbered one of said first stage arrays, a list of connection path pair identifier worDs, according to said block design, through said links to said second stage for array pairs with each other first stage switching array, each identifier including identification of an output terminal on said lowest numbered one of said first stage arrays, identification of one of said second stage switching arrays, and identification of an output terminal on the other one of said first stage arrays in the same first stage pair of arrays, determining an identification of a selected first stage first switching array which is to be paired with a selected second switching array of the same stage, finding the difference between said first and second array identifier numbers, securing from said table the identifier word corresponding to the one of said other first stage arrays having a number equal to said difference, and adding a subtrahend of the difference determination to the second stage array identifier in said corresponding word for finding, as a sum, the identification of a connecting one of said second stage arrays which is to be employed for pairing the selected first stage arrays.
Claim 8
Dependent Claim
145 words
In combination, a first stage of v switching arrays each including nr output connections, where n is a real positive integer at least equal to 1, a second stage of b switching arrays each including nk input connections, and means for interconnecting output connections for each different pair of said v switching arrays to inputs of predetermined ones of said b second stage arrays to provide lambda interconnection circuit pairs between each of said first stage array pairs and said second stage, said interconnecting means comprising a plurality of circuit links, each link providing a sole connection between one of said nr output connections and one of said nk input connections, and said links which extend from any one of said v arrays are distributed among said b arrays, in accordance with a solution of a (b,v,r,k lambda )-configuration of a balanced, incomplete, block design.
Claim 9
Dependent Claim
145 words
In combination, a first stage of v switching arrays each including nr output connections, where n is a real positive integer at least equal to 1, a second stage of b switching arrays each including nk input connections, and means for interconnecting output connections for each different pair of said v switching arrays to inputs of predetermined ones of said b second stage arrays to provide lambda interconnection circuit pairs between each of said first stage array pairs and said second stage, said interconnecting means comprising a plurality of circuit links, each link providing a sole connection between one of said nr output connections and one of said nk input connections, and said links which extend from any one of said v arrays are distributed among said b arrays, in accordance with a solution of a (b,v,r,k lambda )-configuration of a balanced, incomplete, block design.
Claim 10
Dependent Claim
45 words
The combination in accordance with claim 5 in which each input connection of each said first stage switching array is a time division multiplex signal circuit including a plurality of sequential time slot signal channels recurring at a predetermined time division multiplex signal frame rate.
Claim 11
Dependent Claim
43 words
The combination in accordance with claim 5 in which there are provided an additional stage of plural switching arrays, and means for connecting a different output of each array of said additional stage to an input of each of said first stage arrays.
Claim 12
Dependent Claim
43 words
The combination in accordance with claim 5 in which there are provided an additional stage of plural switching arrays, and means for connecting said additional stage arrays to one of said first and second stages in accordance with a balanced, incomplete, block design.
Claim 13
Dependent Claim
40 words
The combination in accordance with claim 5 in which each of said arrays of at least one of said stages is a multistage switching network having its stages connected to one another in accordance with a balanced, incomplete, block design.
Claim 14
Dependent Claim
58 words
The combination in accordance with claim 5 in which said interconnecting means comprises at least an additional stage of plural switching arrays each having input connections and output connections, first means coupling said additional stage input connections to said first stage output connections, and second means coupling said additional stage output connections to said second stage input connections.
Claim 15
Dependent Claim
56 words
The combination in accordance with claim 5 in which said interconnecting means comprises time slot interchanging means having input connections and output connections, first means for coupling said interchanging means input connections to said first stage array output connections, and second means for coupling said interchanging means output connections to said second stage array input connecTions.
Claim 16
Dependent Claim
31 words
The combination in accordance with claim 11 in which said first and second coupling means include link connections to said first and second stages which are mirror images of one another.
Claim 17
Dependent Claim
41 words
The combination in accordance with claim 11 in which said first and second coupling means each includes at least one additional stage of switching arrays coupled to said first and second stages, respectively, in accordance with a balanced, incomplete, block design.
Claim 18
Dependent Claim
87 words
The combination in accordance with claim 13 in which there are provided in each of said first and second coupling means means for detecting in one of said stages, except a stage immediately adjacent to said time slot interchanging means, one of said interconnection circuit pairs having both circuits thereof in the same array of said one stage, and means for bypassing said one interconnection circuit pair from said same array around the remaining stages of said first or second coupling means to said time slot interchanger.
Claim 19
Dependent Claim
29 words
The combination in accordance with claim 5 in which said block design is a symmetric design in which b and v are equal, and r and k are equal.
Claim 20
Dependent Claim
23 words
The combination in accordance with claim 15 in which lambda is equal to 1, and said block design is a finite projective plane.
Claim 21
Dependent Claim
15 words
The combination in accordance with claim 15 in which v and k are not equal.
Claim 22
Dependent Claim
16 words
The combination in accordance with claim 15 in which k is greater than lambda plus 1.
Claim 23
Dependent Claim
16 words
The combination in accordance with claim 15 in which v is greater than lambda plus 2.
Claim 24
Dependent Claim
19 words
The combination in accordance with claim 15 in which v is 7, k is 3, and lambda is 1.
Claim 25
Dependent Claim
19 words
The combination in accordance with claim 15 in which v is 15, k is 7, and lambda is 3.
Claim 26
Dependent Claim
19 words
The combination in accordance with claim 15 in which v is 85, k is 21, and lambda is 5.
Claim 27
Dependent Claim
43 words
The combination in accordance with claim 15 in which each array of said first stage includes a group of crosspoint switching matrices, each matrix having output connections coupled by said interconnecting means to said second stage in accordance with said symmetric block design.
Claim 28
Dependent Claim
59 words
The combination in accordance with claim 23 in which each of said groups of matrices includes n matrices having k output connections, each second stage array has kn input connections, and said solution is a difference set solution of said symmetric block design for each of such first stage groups and it is replicated n times for such group.
Claim 29
Dependent Claim
36 words
The combination in accordance with claim 24 in which each array of said second stage is a multistage network having the stages thereof interconnected in accordance with a balanced, incomplete, block design having kn input connections.
Claim 30
Independent Claim
218 words
A method for selecting crosspoint switches for connecting circuit path pairs in switching arrays of a multistage switching network wherein a first and a second stage, each including a plurality of switching arrays, are interconnected by circuit links arranged in accordance with a symmetrical, balanced, incomplete, block design, the switch selection being controlled by a data processing machine including a memory and operable in accordance with a program of stored instructions, said memory having stored therein a table of three-character words identifying for a first array of a first one of said stages and for all other first stage arrays with which said first array can be paired the array output terminals that must be used to converge link paths from such array pair to a common second stage array, said method comprising the steps of: identifying the difference between array numbers of two first stage arrays to be paired, entering said table at an array number corresponding to said difference, adding to the second stage array number, at the table entry, the subtrahenD previously used to get the difference, and initiating a selection of crosspoint switches in the two first stage arrays to connect the terminals indicated at the table entry, of the two paired arrays to the second stage array number resulting from the adding step.
Claim 31
Independent Claim
218 words
A method for selecting crosspoint switches for connecting circuit path pairs in switching arrays of a multistage switching network wherein a first and a second stage, each including a plurality of switching arrays, are interconnected by circuit links arranged in accordance with a symmetrical, balanced, incomplete, block design, the switch selection being controlled by a data processing machine including a memory and operable in accordance with a program of stored instructions, said memory having stored therein a table of three-character words identifying for a first array of a first one of said stages and for all other first stage arrays with which said first array can be paired the array output terminals that must be used to converge link paths from such array pair to a common second stage array, said method comprising the steps of: identifying the difference between array numbers of two first stage arrays to be paired, entering said table at an array number corresponding to said difference, adding to the second stage array number, at the table entry, the subtrahenD previously used to get the difference, and initiating a selection of crosspoint switches in the two first stage arrays to connect the terminals indicated at the table entry, of the two paired arrays to the second stage array number resulting from the adding step.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |