Detection of errors in shift register sequences

Claim 3

The method in accordance with claim 1 wherein the shift register sequence has a length of k bits, k being greater than 2n 1 and less than or equal to 2n, said method further comprising the steps of providing said output signal on individual ones of k outputs respectively corresponding to different groups of n+1 adjacent bits in said shift register sequence, and detecting the absence of said output signal on each of said outputs.

Claim 4

In combination, a shift register including n+1 tandemly connected shift register stages, means for shifting successive bits of an n-order shift register sequence through said shift register stages, a plurality of gating circuits, and means connecting the outputs of said shift register stages to individual ones of said gating circuits in unique combinations respectively corresponding to different groups of n+1 adjacent bits in saId shift register sequence.

Claim 5

In combination, a shift register including n+1 tandemly connected shift register stages, means for shifting successive bits of an n-order shift register sequence through said shift register stages, a plurality of gating circuits, and means connecting the outputs of said shift register stages to individual ones of said gating circuits in unique combinations respectively corresponding to different groups of n+1 adjacent bits in saId shift register sequence.

Claim 6

The combination in accordance with claim 3 wherein said unique shift register output connection combinations are each Boolean functions having n+ 1 variables.

Claim 7

The combination in accordance with claim 3 further comprising means for detecting a predetermined combination of output signals from said gating circuits, said predetermined output signal combination indicating the presence of an error in said shift register sequence.

Claim 8

The combination in accordance with claim 5 wherein said detecting means comprises an additional gating circuit connected to the outputs of each of said plurality of gating circuits and responsive to each of said plurality of gating circuits having a like output signal.

Claim 9

In an arrangement for detecting errors in an n-order shift register sequence having a length of k bits, n+1 shift register stages, means connecting said shift register stages in tandem, k gates, means connecting a respective unique combination of the outputs of said stages to each of said gates, said unique combination connected to each said gate corresponding to a different group of n+1 adjacent bits in said sequence, and error indication means connected to a predetermined combination of said gates.

Claim 10

In an arrangement for detecting errors in an n-order shift register sequence having a length of k bits, n+1 shift register stages, means connecting said shift register stages in tandem, k gates, means connecting a respective unique combination of the outputs of said stages to each of said gates, said unique combination connected to each said gate corresponding to a different group of n+1 adjacent bits in said sequence, and error indication means connected to a predetermined combination of said gates.

Claim 11

The arrangement in accordance with claim 7 wherein k is greater than 2n 1 and less than or equal to 2n.

Claim 12

In an arrangement for decoding an n-order shift register sequence; said arrangement including a shift register having n tandemly connected stages, said shift register including a first stage and a last stage, means for connecting said sequence to said first shift register stage and for shifting said sequence through successive ones of said tandemly connected shift register stages, a plurality of successional gating circuits including a first and last gating circuit, and means connecting individual unique combinations of the outputs of said shift register stages to each of said gating circuits, such that individual ones of said gating circuits are enabled in succession as said sequence is shifted through said shift register stages; the combination for detecting errors in said shift register sequence comprising, an additional stage tandemly connected to said last shift register stage, means for connecting the output of said additional stage to said first gating circuit in the same manner as the output of said last shift register stage is connected to said last gating circuit, means connecting the output of said additional stage to each of the other of said gating circuits in the same pattern as the output of said last shift register stage is connected to the immediately preceding one of said gating circuits, and means responsive to a predetermined output from said gating circuits.

Claim 13

In an arrangement for decoding an n-order shift register sequence; said arrangement including a shift register having n tandemly connected stages, said shift register including a first stage and a last stage, means for connecting said sequence to said first shift register stage and for shifting said sequence through successive ones of said tandemly connected shift register stages, a plurality of successional gating circuits including a first and last gating circuit, and means connecting individual unique combinations of the outputs of said shift register stages to each of said gating circuits, such that individual ones of said gating circuits are enabled in succession as said sequence is shifted through said shift register stages; the combination for detecting errors in said shift register sequence comprising, an additional stage tandemly connected to said last shift register stage, means for connecting the output of said additional stage to said first gating circuit in the same manner as the output of said last shift register stage is connected to said last gating circuit, means connecting the output of said additional stage to each of the other of said gating circuits in the same pattern as the output of said last shift register stage is connected to the immediately preceding one of said gating circuits, and means responsive to a predetermined output from said gating circuits.