Error control arrangement for information comparison

Claim 2

Apparatus for providing error control for information comparison comprising storage means for storing a data key word encoded in an m-bitburst error correcting code, means for comparing the information portion of said data key word retrieved from said first storage means with an externally supplied master key word, means for decoding said data key word, means responsive to said decoding means for determining a first condition that no error is detected in said data key word, if such condition exists, means responsive to said comparing means and said decoding means for determining a second condition that the most significant digit position E1 of said data key word which is detected as being in error follows, in descending order of digit significance, the most significant digit position P1 in which said data key word and said master key word differ, if such second condition exists, an output circuit, and means responsive to said comparing means and to either said first condition or said second condition for applying a signal to said output circuit indicating whether the value of the data key word bit in position P1 is greater than, equal to, or less than the value of the corresponding bit in the master key word, thereby indicating that the data key word is respectively greater than, equal to, or less than the master key word.

Claim 3

Apparatus as in claim 1 further comprising means responsive to said comparing means and said decoding means for determining a third condition that position P1 follows, in descending order of digit significance, the position E1, if such third condition exists, means responsive to said comparing means and to said decoding means for determining a fourth condition that an error is detected in position E1 of said data key word but no differences between said data key word and said master key word are detected, if such fourth condition exists, means responsive to the presence of a logical ''''1'''' in the master key word position corresponding to position E1 and to either said third condition or said fourth condition for applying a signal to said output circuit indicating that said data key word is less than said master key word, and means responsive to the presence of a logical ''''0'''' in the master key word position corresponding to position E1 and to either said third condition or said fourth condition for applying a signal to said output circuit indicating that said data key word is greater than said master key word.

Claim 4

Apparatus as in claim 2 further comprising means responsive to said comparing means and said decoding means for determining a fifth condition that the position E1 coincides with the position P1, if such fifth condition exists, means responsive to said comparing means, said decoding means, and said fifth condition for locating the next position Pi among the M-1 positions following position P1 in descending order of digit significance in which either said data key word and said master key word differ and no error has occurred or said data key word and said master key word match and an error has occurred, if such a position Pi exists, means responsive to said fifth condition, to the locating of position Pi, and to the presence of a logical ''''1'''' in the master key word position corresponding to position Pi for applying a signal to said output circuit indicating that said data key word is less than said master key word, and means responsive to said fifth condition, to the locating of position Pi, and to the presence of a logical ''''0'''' in the master key word position corresponding to position Pi for applying a signal to said output circuit indicating said data key word is greater than said master key word.

Claim 5

Apparatus as in claim 3 further comprising means responsive to said fifth condition and to a failure to locate position Pi for applying a signal to said output circuit indicating whether the value of the data key word bit in position P2 - the position next following the position P1 + M-1 in descending order of digit significance in which said data key word and said master key word differ - is greater than, equal to, or less than the value of the corresponding bit in said master key word, whereby indicating that the data key word is respectively greater than, equal to, or less than said master key word.

Claim 6

ApParatus for providing error control for information comparison comprising first storage means for storing a data key word encoded in an m-bit-burst error correcting code, first comparing means for comparing the information position of said data key word retrieved from said first storage means with an externally supplied master key word, second storage means responsive to said first comparing means for storing the identity of the most significant digit position P1 in which said data key word and said master key word differ if any, third storage means responsive to said first comparing means for storing an indication R1 of whether the value of the data key word bit in position P1 is greater than, equal to, or less than the value of the corresponding bit in the master key word, a decoder connected to said first storage device for decoding said data key word to generate therefrom either an indication of the most significant digit position E1 of said data key word which is in error and an error pattern word or an indication that no error is present in said data key word, second comparing means responsive to said decoder and said second storage means for generating a first signal if E1 > P1, indicating that E1 follows P1 in position, reading in descending order of digit significance, for generating a second signal if E1 < P1, indicating that E1 precedes P1 in position, and for generating a third signal if E1 P1, indicating that E1 corresponds in position to P1, an output circuit, and means responsive either to an indication of no error from said decoder or to said first signal for applying R1 to said output circuit, thereby indicating that said data key word is greater than, equal to, or less than said master key word if the data key word bit in position P1 is respectively greater than, equal to, or less than the corresponding bit in said master key word.

Claim 7

ApParatus for providing error control for information comparison comprising first storage means for storing a data key word encoded in an m-bit-burst error correcting code, first comparing means for comparing the information position of said data key word retrieved from said first storage means with an externally supplied master key word, second storage means responsive to said first comparing means for storing the identity of the most significant digit position P1 in which said data key word and said master key word differ if any, third storage means responsive to said first comparing means for storing an indication R1 of whether the value of the data key word bit in position P1 is greater than, equal to, or less than the value of the corresponding bit in the master key word, a decoder connected to said first storage device for decoding said data key word to generate therefrom either an indication of the most significant digit position E1 of said data key word which is in error and an error pattern word or an indication that no error is present in said data key word, second comparing means responsive to said decoder and said second storage means for generating a first signal if E1 > P1, indicating that E1 follows P1 in position, reading in descending order of digit significance, for generating a second signal if E1 < P1, indicating that E1 precedes P1 in position, and for generating a third signal if E1 P1, indicating that E1 corresponds in position to P1, an output circuit, and means responsive either to an indication of no error from said decoder or to said first signal for applying R1 to said output circuit, thereby indicating that said data key word is greater than, equal to, or less than said master key word if the data key word bit in position P1 is respectively greater than, equal to, or less than the corresponding bit in said master key word.

Claim 8

Apparatus as in claim 5 further comprising fourth storage means for storing said master key words, means responsive to said second signal and to the presence of a logical ''''1'''' in the master key word position corresponding to position E1 for applying a signal to said output circuit indicating that said data key word is less than said master key word, and means responsive to said second signal and to the presence of a logical ''''0'''' in the master key word position corresponding to position E1 for applying a signal to said output circuit indicating that said data key word is greater than said master key word.

Claim 9

Apparatus as in claim 6 further comprising fifth storage means responsive to said first comparing means for storing indications of those digit positions of the M-1 digit positions next following position P1 in descending order of digit significance in which said data key word and said master key word differ, means responsive to said decoder and to said fifth storage means for locating the next position Pi among the M-1 positions following position P1 in descending order of digit significance in which either said data key word and said master key word differ and no error has occurred or said data key word and said master key word match and an error has occurred, if such a position Pi exists, means responsive to the locating of position Pi and to the presence of a logical ''''1'''' in the master key word position corresponding to position Pi for applying a signal to said output circuit indicating that said data key word is less than said master key word, and means responsive to the locating of position Pi and to the presence of a logical ''''0'''' in the master key word position corresponding to position Pi for applying a Signal to said output circuit indicating that said data key word is greater than said master key word.

Claim 10

Apparatus as in claim 7 further comprising sixth storage means responsive to said first comparing means for storing an indication R2 of whether the value of the data key word bit in position P2 - the position next following the position P1 + M-1 in descending order of digit significance in which said data key word and said master key word differ - is greater than, equal to, or less than the value of the corresponding bit in said master key word, and means responsive to a failure to locate position Pi for applying R2 to said output circuit, thereby indicating that said data key word is greater than, equal to, or less than said master key word if the data key word bit in position P2 is respectively greater than, equal to, or less than the corresponding bit in said master key word.