Shift register clocking at high speeds where parallel operation is needed

Claim 1

A digital integrator comprising: a plurality of shift registers being connected so as to operate in parallel; a master clock being connected to drive a high speed clock and a low speed clock; said high speed clock and said low speed clock being gated to supply a single phase clock signal to control said plurality of shift registers wherein said high speed clock is gated to said plurality of shift registers to the exclusion of said low speed clock while when said low speed clock is gated to said plurality of shift registers said high speed clock is blocked; a data line being connected to said plurality of shift registers for supplying parallel data to said plurality of shift registers; a data gate being connected to each of said plurality of shift registers for gating in data and for resetting said plurality of shift registers; each of said plurality of shift registers having an output; each of said plurality of shift registers comprising a plurality of high speed shift registers connected to operate in parallel each of said high speed shift registers having an output, a first input, a second input complementary to said first input, a first phase clock input, and a second phase clock input; a plurality of clock means for receiving said single phase clock signal and for generating a first phase clock signal and a second phase clock signal which are approximately complementary in phase; said first and second clock signals being connected to said first and second phase clock inputs respectively; said clock means being located relative to said high speed shift registers to minimize cross talk data means connected to said data line for receiving said parallel data and for complementing said parallel data; said data means being coupled in parallel to said plurality of high speed shift registers first and second inputs.