US3700819A
Expired / Lapsed
US
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Time division switching system with time slot interchange
Assignee: AT&T Inc
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Filing: 1970-12-07
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Granted: 1972-10-24
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Expires: 1990-12-07
Abstract
Abstract A multistage network for permuting an input sequence of signals is described. Typically, this sequence corresponds to time division multiplexed communication signals. The overall permuting is accomplished by partially permuting the signals at each stage of selectively delaying these signals in accordance with stored control information. Techniques are described for deriving the required control information and a number of alternate embodiments for the delay circuitry are presented.
Inventors
- 👤 Michael Jay Marcus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:56
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/08
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
151 words
Apparatus for permuting the order oF a sequence of N input signals comprising A. an ordered plurality of stages, each arranged to perform at least part of said permuting, each of said stages comprising 1. a memory storing control signals partially indicative of said permuting, 2. serial delay means comprising at least one delay element, 3. a time division signal path having an input and an output, and 4. means responsive to said control signals for selectively introducing said delay means into said signal path at at least one point between said input and said output, thereby to permute signals applied at said input to an extent indicated by said control signals, B. means for invariantly connecting the output of each stage except the last to the input of the immediately following stage, and C. means for applying said input signals at the input of the first of said ordered stages.
Claim 2
Dependent Claim
151 words
Apparatus for permuting the order oF a sequence of N input signals comprising A. an ordered plurality of stages, each arranged to perform at least part of said permuting, each of said stages comprising 1. a memory storing control signals partially indicative of said permuting, 2. serial delay means comprising at least one delay element, 3. a time division signal path having an input and an output, and 4. means responsive to said control signals for selectively introducing said delay means into said signal path at at least one point between said input and said output, thereby to permute signals applied at said input to an extent indicated by said control signals, B. means for invariantly connecting the output of each stage except the last to the input of the immediately following stage, and C. means for applying said input signals at the input of the first of said ordered stages.
Claim 3
Dependent Claim
9 words
serial delay means comprising at least one delay element,
Claim 4
Dependent Claim
9 words
serial delay means comprising at least one delay element,
Claim 5
Dependent Claim
55 words
Apparatus according to claim 1 wherein said sequence of input signals comprises N bytes representing information in N consecutive input time slots, and wherein said delay means in at least one of said stages comprises an N-byte register for storing said N bytes in said input signals in an order determined by said control signals.
Claim 6
Dependent Claim
8 words
a shift register having m bytes of storage,
Claim 7
Dependent Claim
8 words
a shift register having m bytes of storage,
Claim 8
Dependent Claim
12 words
a time division signal path having an input and an output, and
Claim 9
Dependent Claim
12 words
a time division signal path having an input and an output, and
Claim 10
Dependent Claim
92 words
first selecting means comprising means responsive to a subset of said control signals for selectively introducing said delay means into said signal path at at least one point between said input and said output, thereby to permute signals applied at said input to an extent indicated by said subset of said control signals, C. means for invariantly connecting the output of each stage except the last to the input of the immediately following stage, and D. means for applying said input signals at the input of the first of said ordered stages.
Claim 11
Dependent Claim
92 words
first selecting means comprising means responsive to a subset of said control signals for selectively introducing said delay means into said signal path at at least one point between said input and said output, thereby to permute signals applied at said input to an extent indicated by said subset of said control signals, C. means for invariantly connecting the output of each stage except the last to the input of the immediately following stage, and D. means for applying said input signals at the input of the first of said ordered stages.
Claim 12
Dependent Claim
15 words
means for parallel transferring the contents of said first register to said shift register, and
Claim 13
Dependent Claim
15 words
means for parallel transferring the contents of said first register to said shift register, and
Claim 14
Dependent Claim
26 words
Apparatus according to claim 2 wherein said means for introducing said delay means comprises means for selecting among bytes in said N-byte sequence of input signals.
Claim 15
Dependent Claim
12 words
a time division signal path having an input and an output, and
Claim 16
Dependent Claim
12 words
a time division signal path having an input and an output, and
Claim 17
Dependent Claim
82 words
means responsive to said control signals for selectively introducing said delay means into said signal path at at least one point between said input and said output, thereby to permute signals applied at said input to an extent indicated by said control signals, B. means for invariantly connecting the output of each stage except the last to the input of the immediately following stage, and C. means for applying said input signals at the input of the first of said ordered stages.
Claim 18
Dependent Claim
82 words
means responsive to said control signals for selectively introducing said delay means into said signal path at at least one point between said input and said output, thereby to permute signals applied at said input to an extent indicated by said control signals, B. means for invariantly connecting the output of each stage except the last to the input of the immediately following stage, and C. means for applying said input signals at the input of the first of said ordered stages.
Claim 19
Dependent Claim
47 words
means for shifting out the contents of said shift register, and B. said first selecting means comprises means for distributing a subset of m bytes of the signals appearing at the input of said signal path to selected ones of said m bytes of said first register.
Claim 20
Dependent Claim
47 words
means for shifting out the contents of said shift register, and B. said first selecting means comprises means for distributing a subset of m bytes of the signals appearing at the input of said signal path to selected ones of said m bytes of said first register.
Claim 21
Dependent Claim
99 words
Apparatus according to claim 3 wherein said means for selecting comprises A. a plurality of AND gates, each having a plurality of input leads and one output lead, B. first input means for applying signals in said input sequence to each of said AND gates, C. second input means for applying control signals to each of said AND gates, thereby to enable signals in said input sequence to appear on selected ones of said output leads of said AND gates, and D. means for connecting said output leads of said AND gates to corresponding bytes of said N-byte register.
Claim 22
Dependent Claim
31 words
Apparatus for permuting the order of a sequence of N input signals comprising A. a memory storing control signals indicative of said permuting, B. an ordered plurality of stages, each comprising
Claim 23
Dependent Claim
31 words
Apparatus for permuting the order of a sequence of N input signals comprising A. a memory storing control signals indicative of said permuting, B. an ordered plurality of stages, each comprising
Claim 24
Dependent Claim
27 words
Apparatus according to claim 5 further comprising means for periodically reading said control signals from said memory and applying said control signals to said plurality of stages.
Claim 25
Dependent Claim
31 words
Apparatus according to claim 6 wherein said memory comprises a plurality of segments, each of said segments being arranged to store control signals associated with a corresponding one of said stages.
Claim 26
Dependent Claim
33 words
Apparatus according to claim 7 further comprising means for generating said control signals and means for applying to each of said segments generated control signals for controlling said corresponding one of said stages.
Claim 27
Dependent Claim
15 words
Apparatus according to claim 8 wherein said means for generating comprises a programmed data processor.
Claim 28
Dependent Claim
105 words
Apparatus according to claim 5 wherein in at least one of said stages A. said delay means comprises k ordered shift registers, each of which comprises an input, m bytes of storage, and an output, B. said first selecting means comprises means for distributing signals appearing at said input of said signal path to inputs of selected ones of said k shift registers, further comprising C. a source of shift signals for periodically shifting the contents of said k shift registers toward said outputs of said shift registers, and D. means for selectively delaying the signals appearing at the outputs of said k shift registers.
Claim 29
Dependent Claim
8 words
Apparatus according to claim 10 wherein k.m N.
Claim 30
Dependent Claim
10 words
Apparatus according to claim 11 wherein k m N .
Claim 31
Dependent Claim
8 words
Apparatus according to claim 10 wherein k 2.
Claim 32
Dependent Claim
82 words
Apparatus according to claim 13 wherein said means for selectively delaying comprises A. first and second cascaded delay units each having an input and units of delay, and an output, B. a switch alternately connecting the output of the second of said shift registers to the input of the first of said delay units and output of said second delay unit, and C. means connecting the output of the first of said shift registers to the input of said second delay unit.
Claim 33
Dependent Claim
73 words
Apparatus according to claim 11 wherein said means for selectively delaying comprises k-1 ordered delay units connected in cascade, means connecting the output of the ith of said shift registers, i 1, 2, 3, . . . , k-1, to the output of the ith of said ordered delay units, and means connecting the output of the kth of said shift registers to the input of the (k-1)th of said ordered delay units.
Claim 34
Dependent Claim
26 words
Apparatus according to claim 5 wherein said plurality of stages comprises two stages, and wherein at the second of said stages A. said delay means comprises
Claim 35
Dependent Claim
23 words
Apparatus according to claim 13 wherein said means for selectively delaying comprises means for merging the contents of both of said shift registers.
Claim 36
Dependent Claim
43 words
Apparatus according to claim 5 wherein in at least one of said stages said first selecting means comprises means for introducing said delay means in such manner as to sort a subset of the signals appearing at the input of said signal path.
Claim 37
Dependent Claim
27 words
Apparatus according to claim 18 wherein said first selecting means comprises means for sorting subsets comprising two consecutive signals appearing at said input of said signal path.
Claim 38
Dependent Claim
77 words
Apparatus according to claim 18 wherein in at least another of said stages A. said delay means comprises k ordered shift registers, each of which comprises an input and an output, B. said first selecting means comprises means for directing signals appearing at said input of said signal path to inputs of selected ones of said k shift registers, further comprising C. means for selectively delaying the signals appearing at the outputs of said k shift registers.
Claim 39
Dependent Claim
29 words
Apparatus according to claim 20 wherein k 2 and said means for selectively delaying comprises means for merging the signals appearing at the outputs of said two shift registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |