Capture combination system

Claim 2

In a capture combination system having a plurality of pistons and a plurality of stops, said pistons being arranged in a plurality of groups of a number of pistons each, each group of pistons being associated with a corresponding group of stops, and each piston, when actuated, being operable to establish a preselected combination of stops of the asSociated group of stops, the improvement comprising: first input means receiving an input in response to each piston actuation, second input means receiving an input in response to each stop selection, cyclic addressing means for repetitively addressing said first input means in time sequence to recognize and identify an actuated piston and the group thereof, and for addressing said second input means in time sequence to derive stop bit data identifying the stop selections of pre-selected combinations, in accordance with said groups of stops, an operating memory having a plurality of bit storage positions assigned in accordance with each piston and its associated group of stops for storing the stop bit data identifying the pre-selected stops combination for each piston of said group of pistons, said cyclic addressing means addressing said second input means in response to identification of an actuated piston in accordance with addressing of said first input means for deriving from said second input means the stop bit data identifying the pre-selected stops combination for the groups of stops associated with the actuated piston, and gating means enabled in accordance with the identification of an actuated piston to enter into the assigned bit positions of said operating memory, the stop bit data derived from said second input means for the group of stops associated with the identified, actuated piston.

Claim 3

The improvement in capture combination system as recited in claim 1 wherein: said second input means is responsive to the stops input selections to define at least two input data bit groups corresponding to the stops input selections for each group of stops associated with said pistons, and said gating means is enabled in accordance with the identification of an actuated piston to respond to said at least two data bit groups, in succession, in the corresponding successive cycles of said cyclic addressing means in addressing said second input means, to enter the stop bit data of each said data bit group into the assigned bit positions of said operating memory during an interval in the corresponding successive cycles of said cyclic addressing means, wherein the interval in each said successive cycle is selected in accordance with the availability of the respectively associated bit storage locations of said operating memory for entry and storage therein of the data bit group.

Claim 4

The improvement in a capture combination system as recited by claim 2 wherein: said groups of pistons include a plurality of groups of divisional pistons, each of said divisional piston groups having associated therewith a corresponding group of stops and each said divisional piston being operable to establish a pre-selected combination of the stops of that associated group, and at least one group of said pistons includes general pistons for which the associated group of stops comprises the totality of stops in the system, each general piston of said group of general pistons being operable to establish a pre-selected combination of the totality of stops of the system.

Claim 5

The improvement in a capture combination system as recited in claim 3 wherein: said second input means defines two input data bit groups for each group of divisional stops, and a number of data bit groups for said general stops corresponding to the total of data bit groups for the total of the divisional stop groups, said cyclic addressing means addresses said second means in a number of successive cycles respectively corresponding to the total of said data bit groups in response to each piston actuation, and said gating means is enabled for transfer of stop bit data during the cycles of said addressing means in which the data bit groups associated with an actuated, identified piston are addressed.

Claim 6

The improvement in a capture combination system as recited in claim 1 wherein there is further provided: enabling means for normally enabling said first input meanS for identification of an actuated piston in response to addressing of said first input means, and means for recognizing actuation of a piston for enabling identification of selected stops in response to addressing of said second input means.

Claim 7

The improvement in a capture combination system as recited in claim 1, wherein: said cyclic addressing means addresses said first input means to identify the group of a piston actuated to establish stop combinations in accordance with the pre-selected stop combinations of the associated group of stops stored in said operating memory, said gating means is enabled in accordance with the identification of said piston actuated to establish stop combinations to readout from said operating memory the stop bit data for each said group of stops associated with the identified, actuated piston, and there is further provided: stop actuators for selectively setting the stops of the systems in accordance with the stop selections, and decoding means addressed by said cyclic addressing means for enabling energization of said stop actuators in groups in accordance with each said group of stops associated with the identified group of pistons and for energizing the stop actuators of each said group in accordance with the stop bit data readout from said operating memory and identifying the preselected stop combinations of said group.

Claim 8

The improvement in a capture combination system as recited in claim 1 wherein there is further provided: enabling means for enabling entry of said stop selections in said groups thereof into said operating memory as associated with an actuated, identified piston in response to a set command generated simultaneously with actuation of said identified piston.

Claim 9

The improvement in a capture combination as recited in claim 1 wherein there is further provided: register means responsive to identification of an actuated piston to register an identification of the group of that piston and of the piston, said operating memory includes a plurality of sections, and said gating means includes section selection means responsive to the piston group identification of said register means to select the section of said operating memory corresponding to an identified, actuated piston, and to the piston identification of said register means to define the portion of each section containing the information bit storage positions associated with said identified, actuated piston.

Claim 10

The improvement in a capture combination system as recited in claim 1 wherein there is further provided an external memory for storing the stop selections entered in said operating memory, further comprising: means operable in synchronism with the recirculation of said operating memory to define a periodic gating interval for addressing the storage bit positions of said operating memory individually and in succession for successive cycles of recirculation thereof, control means for rendering said periodic gating interval means operable to effect transfer of data bits between said operating memory and said external memory, buffer storage means for storing data bits read from said operating memory for recording in said external memory, and for storing bits read from said external memory for entry into the assigned bit positions of said operating memory, and said gating means being responsive to said periodic gating interval means when actuated by said transfer control means for a record operation, to transfer a data bit during each said periodic gating interval, from said operating memory, and the plurality of data bits stored therein in succession for each recirculation thereof, to said buffer storage means for recording in said external memory, and, for a read and entry operation, to transfer data bits in succession as read from said external memory, to said buffer storage means for entry into said assigned bit positions of said operating memory, in succession, and during said periodic Gating interval for each recirculation thereof.

Claim 11

A capture combination system as recited in claim 9 wherein there is further provided: further buffer storage means operable to store a data bit read from said external memory within the time duration of the recirculation of said operating memory for entry of that data bit into said operating memory in the next successive recirculation cycle thereof.

Claim 12

A capture combination system as recited in claim 9 wherein there is further provided: means for generating a strobe pulse in response to each periodic gating interval, means for recording each strobe pulse in said external memory in timed relationship with the recording of each data bit therein, strobe pulse buffer storage means for storing each strobe pulse, in succession, as generated by said generating means in a record operation, and for storing each strobe pulse, in succession, as read from said external memory, and said gating means being responsive to said periodic gating interval means, when actuated by said transfer control means for a record operation, to store a strobe pulse in said first strobe pulse buffer storage means for recording in said external memory, and, for a read and entry operation, to transfer each strobe pulse read from said external memory to said strobe pulse buffer storage means.

Claim 13

The improvement in a capture combination system as recited in claim 11 wherein there is further provided: further strobe pulse buffer storage means operable to store a further strobe pulse read from said external memory within the time duration of the recirculation of said operating memory, and said further strobe pulse buffer storage means being enabled by said strobe pulse buffer storage means upon receipt thereby of a strobe pulse, to receive said further strobe pulse, and upon receipt of said further strobe pulse, being operable to disable said data bit buffer storage means and to enable said further data bit buffer storage means for receipt thereby of a further data bit, as read from said external memory within the time duration of the recirculation of said operating memory.

Claim 14

The improvement in a capture combination system as recited in claim 1 wherein: said operating memory comprises a plurality of groups of plural recirculating shift registers, said groups of pistons include a plurality of groups of divisional pistons, each divisional piston group being associated with a different group of said stops, and at least one group of general pistons, each general piston group being associated with a group of stops comprising the totality of stops in the system, and said gating means includes shift register selection means responsive to the identification of the group of an actuated piston to select the corresponding group of plural shift registers, and to the identification of the actuated piston of that group to select the shift register of the group having the assigned bit positions corresponding to the group of stops associated with the actuated piston.

Claim 15

The improvement in a capture combination system as recited in claim 13 wherein: said gating means is responsive to the identification of an actuated divisional piston to select the portion of the selected shift register having the assigned bit positions corresponding to the group of stops associated with the actuated divisional piston.

Claim 16

The improvement in a capture combination system as recited in claim 14 wherein: each shift register of the group thereof selected for general pistons has a number of bit positions corresponding to the totality of stops of the system.

Claim 17

The improvement in a capture combination system as recited in claim 15 wherein: each shift register of the group thereof selected for divisional pistons has a number of bit positions corresponding to the totality of stops of the system ordered in a plurality of time division groups in accordance with the recirculation of said shift registers, and SAID addressing means enables said gating means in accordance with the identification of an actuated divisional piston and the corresponding time division group in relation to the recirculation time of said shift register for accessing the bit storage positions assigned to the stops of the group associated with the actuated divisional piston.

Claim 18

The improvement in a capture combination system as recited in claim 16, wherein: said cyclic addressing means addresses said first input means to identify the group of a piston actuated to establish stop combinations in accordance with data bits stored in said operating memory and identifying the pre-selected stop combinations of the associated group of stops, said gating means is enabled in accordance with the identification of said piston actuated to establish stop combinations, to read out from said operating memory the stop bit data for each said group of stops associated with the identified, actuated piston, and there is further provided: stop actuators for selectively setting the stops of the system in accordance with the stop selections, and decoding means addressed by said cyclic addressing means for enabling energization of said stop actuators in groups in accordance with each said group of stops associated with the identified group of pistons and for energizing the stop actuators of each said group in accordance with the stop bit data readout from said operating memory and identifying the pre-selected stop combinations of said group.

Claim 19

The improvement in a capture combination system as recited in claim 1 wherein there is further provided: enabling means for enabling entry of said stop selections in said groups thereof into said operating memory as associated with an actuated, identified piston in response to a set command generated simultaneously with actuation of said identified piston.

Claim 20

A capture combination system for an organ having a plurality of pistons arranged in groups of divisional pistons and a plurality of stops arranged in groups corresponding to said divisional piston groups, each divisional piston being operable to establish a pre-selected combination of stops of the group associated with that piston, comprising: first input means having a plurality of input terminals corresponding to said plurality of pistons and arranged for input addressing in accordance with said groups of pistons, second input means having a plurality of input terminals corresponding to said plurality of stops and arranged for input addressing in accordance with said groups of stops, cyclic addressing means for repetitively addressing said first input means in time sequence to recognize and identify an actuated piston and the group thereof, and for addressing said second input means in time sequence to derive stop bit data identifying the stop selections of pre-selected combinations, in accordance with said groups of stops, an operating memory having a section corresponding to each group of divisional pistons and each section having portions corresponding to the pistons of the group, and including in each portion a plurality of bit storage locations assigned to the stops of the group associated with the corresponding piston, said cyclic addressing means addressing said second input means in response to identification of an actuated piston in accordance with addressing of said first input means for deriving from second input means the stop bit data identifying the pre-selected stops combination for the group of stops associated with the actuated piston, and gating means enabled in accordance with the identification of an actuated piston to enter into the assigned bit positions of said operating memory, the stop bit data derived from said second input means for the group of stops associated with the identified, actuated piston.

Claim 21

A capture combination system for an organ having a plurality of pistons arranged in groups of divisional pistons and a plurality of stops arranged in groups corresponding to said divisional piston groups, each divisional piston being operable to establish a pre-selected combination of stops of the group associated with that piston, comprising: first input means having a plurality of input terminals corresponding to said plurality of pistons and arranged for input addressing in accordance with said groups of pistons, second input means having a plurality of input terminals corresponding to said plurality of stops and arranged for input addressing in accordance with said groups of stops, cyclic addressing means for repetitively addressing said first input means in time sequence to recognize and identify an actuated piston and the group thereof, and for addressing said second input means in time sequence to derive stop bit data identifying the stop selections of pre-selected combinations, in accordance with said groups of stops, an operating memory having a section corresponding to each group of divisional pistons and each section having portions corresponding to the pistons of the group, and including in each portion a plurality of bit storage locations assigned to the stops of the group associated with the corresponding piston, said cyclic addressing means addressing said second input means in response to identification of an actuated piston in accordance with addressing of said first input means for deriving from second input means the stop bit data identifying the pre-selected stops combination for the group of stops associated with the actuated piston, and gating means enabled in accordance with the identification of an actuated piston to enter into the assigned bit positions of said operating memory, the stop bit data derived from said second input means for the group of stops associated with the identified, actuated piston.

Claim 22

The improvement in a capture combination system as recited in claim 19 wherein: said second input means is responsive to the stopS input selections to define at least two input data bit groups corresponding to the stops input selections for each group of stops associated with said pistons, and said gating means is enabled in accordance with the identification of an actuated piston in respond to said at least two data bit groups, in succession, in the corresponding successive cycles of said cyclic addressing means in addressing said second input means, to enter the stop bit data of each said data bit group into the assigned bit positions of said operating memory during an interval in the corresponding successive cycles of said cyclic addressing means, wherein the interval in each said successive cycle is selected in accordance with the availability of the respectively associated bit storage locations of said operating memory for entry and storage therein of the data bit group.

Claim 23

A capture combination system as recited in claim 19 wherein the system further includes at least one group of general pistons associated with the group of stops comprising the totality of stops of the system, wherein: said operating memory includes a further section corresponding to said group of general pistons and a portion of that further section corresponding to each general piston, said portion including storage bit positions corresponding to the totality of the stops of the system, and said gating means is enabled in accordance with identification of an actuated general piston to enter the stop bit data for the totality of stops into the assigned stop bit storage positions of the portion corresponding thereto.

Claim 24

A capture combination system as recited in claim 21 wherein: said operating memory comprises a first set of a plural recirculating shift registers for said divisional pistons and a second set of plural recirculating shift registers for said general pistons, said memory section for said general piston group comprising the entirety of said second set of shift registers, and for said divisional piston groups comprising respectively corresponding locations in the plural shift registers of said first set, and said plural shift registers of each set corresponding to the pistons of the groups of divisional and general pistons, respectively, to define said portions of each section of the memory.

Claim 25

A capture combination system as recited in claim 22 wherein: said shift registers comprise recirculating shift registers, controlled to recirculate in synchronism with one another, and said gating means is enabled in accordance with the recycling of said shift registers to define each said portion and the associated bit storage locations as time intervals of the recirculation cycles of the shift registers.

Claim 26

A capture combination system as recited in claim 23 wherein there is further provided: register means responsive to the identification of a piston to select in accordance with the group of that piston the corresponding memory section in accordance with said first and second sets of shift registers, and the corresponding memory portion, and said gating means is further responsive to the identification of a divisional piston group to select the time interval of recirculation for defining the corresponding memory portion.

Claim 27

The improvement in a capture combination system as recited in claim 24 wherein: said cyclic addressing means addresses said first input means to identify the group of a piston actuated to establish stop combinations in accordance with the pre-selected stop combinations of the associated group of stops stored in said operating memory, said gating means is enabled in accordance with the identification of an actuated piston to establish stop combinations, to readout from said operating memory the stop bit data for each said group of stops associated with the identified, actuated piston, and there is further provided: stop actuators for selectively setting the stops of the system in accordance with the stop selections, and decodIng means addressed by said cyclic addressing means for enabling energization of said stop actuators in groups in accordance with each said group of stops associated with the identified group of pistons and for energizing the stop actuators of each said group in accordance with the stop bit data readout from said operating memory and identifying the pre-selected stop combinations of said group.

Claim 28

The improvement in a capture combination system as recited in claim 25 wherein there is further provided: enabling means for enabling entry of said stop selections in said groups thereof into said operating memory as associated with an actuated, identified piston in response to a set command generated simultaneously with actuation of said identified piston.

Claim 29

A capture combination system as recited in claim 23 wherein there is further provided: an external memory for storing the stop selections entered in said operating memory, means operable in synchronism with the recirculation of said sets of shift registers to define a periodic gating interval for addressing said sets in parallel and, within each set, addressing the bit positions of said shift registers individually and in succession for successive cycles of recirculation thereof, for the plurality of shift registers in sequence, control means for rendering said periodic gating interval means operable to effect transfer, in parallel, of data bits between said sets of shift registers and said external memory, buffer storage means for storing data bits read from said sets of shift registers for recording in parallel in said external memory, and for storing bits read in parallel from said external memory for entry, in parallel, into the assigned bit positions of the respectively corresponding sets of shift registers, said gating means being responsive to said periodic gating interval means when actuated by said transfer control means for a record operation, in parallel for said sets of shift registers and sequentially for the plural shift registers of each set, to transfer a data bit during each said periodic gating interval, from said shift registers for the plurality of data bits stored therein, in succession and for each recirculation thereof, to said buffer storage means for recording in said external memory, and, for a read and entry operation, to transfer data bits in succession as read from said external memory, to said buffer storage means for entry into said assigned bit positions of said shift registers in succession, and during said periodic gating interval for each recirculation thereof.

Claim 30

A capture combination system as recited in claim 27 wherein there is further provided: further buffer storage means operable to store a data bit read from said external memory within the time duration of the recirculation of said shift registers, for entry of that data bit into said operating memory in the next successive recirculation cycle thereof.

Claim 31

A capture combination system as recited in claim 27 wherein there is further provided: means for generating a strobe pulse in response to each periodic gating interval, means for recording each strobe pulse in said external memory in timed relationship with the recording of each data bit therein, strobe pulse buffer storage means for storing each strobe pulse, in succession, as generated by said generating means in a record operation, and for storing each strobe pulse, in succession, as read from said external memory, and said gating means being responsive to said periodic gating interval means, when actuated by said transfer control means for a record operation, to store a strobe pulse in said first strobe pulse buffer storage means for recording in said external memory, and, for a read and entry operation, to transfer each strobe pulse read from said external memory to said strobe pulse buffer storage means.

Claim 32

The improvement in a capture combination system as recited in claim 29 wherein there is furtheR provided: further strobe pulse buffer storage means operable to store a further strobe pulse read from said external memory within the time duration of the recirculation of said operating memory, and said further strobe pulse buffer storage means being enabled by said strobe pulse buffer storage means upon receipt thereby of a strobe pulse, to receive said further strobe pulse, and upon receipt of said further strobe pulse, being operable to disable said data bit buffer storage means and to enable said further bit buffer storage means for receipt thereby of a further data bit, as read from said external memory within the time duration of the recirculation of said operating memory.