Adaptable associative memory system

Claim 2

An adaptable associative electronic information storage system comprising: a. an input recognition matrix composed of a multiplicity of electrically identical memory and logic subcircuits containing at least one bit and not more than two bits of memory each and connected in rows and columns; b. a multiplicity of row input conductors each common to only one row of said subcircuits of said input matrix; c. an output selection matrix composed of a multiplicity of electrically identical memory and logic subcircuits containing one bit only of memory each and connected in rows and columns; d. a multiplicity of row output conductors each common to only one row of said subcircuits of said output matrix; e. a multiplicity of control conductors each of which is common to only one column of said subcircuits of said input matrix and to only one column of said subcircuits of said output matrix, including for every column of said matrices a column write conductor and a column erase conductor; f. a plurality of column response conductors each common to only one column of said subcircuits of said input matrix; g. a plurality of column activation conductors each common to only one column of said subcircuits of said output matrix; h. an array of binary signal inverters each connected to respond to the condition of a column response conductor of said input matrix and to control the operation of a column activation conductor of said output matrix, and i. control means adapted to apply to said row output conductor any of a variety of predetermined output condition patterns, including in said variety a nulL output pattern, for association with a selected condition pattern of said input conductors and to establish said association in the memories of a column of said input matrix and a related (by said signal inverter array) column of said output matrix by activation of corresponding erase conductors, write conductors or, in sequence, both.

Claim 3

An electronic information storage system as defined in claim 1 in which: j. said subcircuits of said input matrix contain one and only one bit of memory each; and k. said subcircuits of said input matrix contain one and only one bit of memory each.

Claim 4

An electronic information storage system as defined in claim 1 in which the memory content of each of said subcircuits, both of said input matrix and of said output matrix, are provided by bistable transistor circuits respectively forming part of said subcircuits.

Claim 5

An electronic information storage system as defined in claim 1 in which said control means includes: l. a timing pulse generator; m. a shift register adapted to be advanced one step by pulses generated by said timing pulse generator and comprising a cyclically connected array of memory cells, each of which is associated with a column of said input and output matrices and in one of which one binary signal condition exists while in all the others the opposite binary signal condition exists, said shift register being arranged to propagate said unique binary signal condition progressively and cyclically from one of said cells of said shift register to the next; and n. an array of identical circuits, each of which is associated with one cell of said shift register and with the write and erase conductors of a column of said matrices and the response conductor of said column of said input matrix, as well as with common write and erase conductors of said control means, in such a way that application of a predetermined output pattern for association with a selected condition of said inputs different from all conditions (other than the null pattern) at that time in the memory of some column said input matrix, will be prevented from disturbing columns of said input matrix in which such other conditions are in memory and will be effected only in a column in which a null input pattern is in memory.

Claim 6

An electronic information storage system as defined in claim 4 in which each of said subcircuits associated with said cells of said shift register contain a one bit memory element adapted to indicate whether the corresponding column is occupied by an association (other than null) imposed by said control means.

Claim 7

An electronic information storage system as defined in claim 5 in which each of said subcircuits associated with one of said cells of said shift register also contains an additional one bit memory element adapted to be set by the activation of the corresponding column write conductor, to cause when set the blocking of a timing pulse from said shift register until the pattern, written into the column memory by said energization of said column write conductor, has been removed.

Claim 8

An electronic information storage system as defined in claim 1 in each of the said subcircuits of said input matrix of which: o. there are three AND gates and a one bit memory element adapted (i) to be set by one AND gate having as inputs one of said row input conductors and one of said column write conductors (ii) to be reset by a column erase conductor and (iii) to provide a direct output and an inverse output respectively to the two other AND gates, the first-mentioned of which has for its only other input a connection to said row input conductor and the last-mentioned of which has for its only other input the inverse of the condition of said row input conductor; and p. an OR gate having two inputs, respectively connected to the outputs of said two last-mentioned AND gates, said OR gate having an inverted output connected to one of said column response conductors through a protective diode.

Claim 9

An electronic information storage system as defined in claim 1 in which each of said subcircuits of said output matrix contain two two-input AND gates and a one bit memory element adapted (i) to be set by one AND gate having an input connected to one of said column write conductors and its other input connected to one of said row output conductors (ii) to be reset by one of said column erase conductors and (iii) to supply an output when set to the other of said AND gates, which has its other input connected to one of said column activation conductors and its output connected through a protective diode to said one of said row output conductors.

Claim 10

An electronic information storage system as defined in claim 1 in which: q. said multiplicity of row input conductors includes two conductors common to each row of said subcircuits of said input matrix; r. each pair of row input conductors common to the same row of subcircuits is provided with an entry circuit interconnecting it with a binary signal input conductor and with a ''''disregard'''' conductor the condition of which is adapted to indicate whether the subcircuits of a row are intended to disregard the condition of said binary input conductor, said entry means comprising a pair of AND gates both of which have an input activated by one and the same condition of said disregard conductor, one of which gates has another input which responds directly to the condition of said binary input conductor and defines the conductor connected to the gate output as the direct row input conductor and the other of which gates has another input that responds to the inverse of the condition of said binary input conductor and defines the conductor to which the gate output is connected as the inverse row input conductor; and s. each of said subcircuits of said input matrix contains two one bit memory elements, one of which is adapted to be set by one condition of said binary input conductor in the absence of a disregard signal and the other of which is adapted to be set by the other condition of said binary input conductor in the absence of a disregard signal.

Claim 11

An electronic information storage system as defined in claim 9 in which: t. the first-mentioned of said one bit memory elements in each of said subcircuits of said input matrix is associated (i) with an input AND gate by the output of which said memory element is adapted to be set, said input AND gate having inputs connected respectively to a direct row input conductor and a column write conductor and (ii) with an output AND gate with inputs connected respectively to the direct output (on-mode while set) of said first-mentioned memory element and to an inverse row input conductor for the same row served by said row input conductor, said output AND gate having its output connected through a protective diode to a column response conductor; and u. the other of said one bit memory elements in each of said subcircuits of said input matrix is associated with (i) an input AND gate by the output of which said memory element is adapted to be set, said input AND gate having inputs connected respectively to said inverse row input conductor and to said column write conductor and (ii) with an output AND gate with inputs connected respectively to the direct output of said last-mentioned one bit memory element and to said direct row input conductor, said output AND gate having its output connected through a protective diode to said column response conductor.

Claim 12

An adaptable associative electronic information storage system comprising: a. an input recognition matrix composed of a multiplicity of electrically identical memory and logic subcircuits connected in rows and columns; b. a multiplicity of input conductors each common to only one row of said subcircuits of said input matrix; c. a multiplicity of control conductors each common to only one column of said subcircuits of said input matrix, including for each column a column wriTe conductor, a column erase conductor and a column response conductor; d. an output selection matrix composed of a multiplicity of electrically identical memory and logic subcircuits connected in rows and columns; e. a multiplicity of conductors each common to only one row of said subcircuits of said output matrix including at least an output conductor for each of said rows; f. a multiplicity of control conductors each common to only one column of said subcircuits of said output matrix including at least a column activation conductor for each of said columns; g. an array of binary signal inverters each connected to respond to the condition of a column response conductor of said input matrix and to modify the operation of a column activation conductor of said output matrix; h. a timing pulse generator; i. system control means, including a switch arranged to command a training phase of the system, adapted during such training phase to impose a selected response pattern on said output conductors for writing into a column activated by its column activation conductor, to generate write or erase signals and to block the output of said timing pulse generator during erase signals so generated, said system control means also including a switch arranged to command generation of an erase signal without blocking of timing pulses; and j. a matrix control unit adapted to receive write and erase signals and timing pulses from said system control means, said matrix control unit comprising a linear array of logic and memory subcircuits and having a shift register adapted to advance a column scanning binary signal cyclically step by step through a series of memory cells each in a different one of said last-mentioned subcircuits in response to said timing pulses, said matrix control unit being so constituted as to be adapted to erase the memory of the column of said input matrix indicated by an off-mode signal of a column response conductor during the presence of an erase signal, to write into the memory of an empty column of said input matrix the signals appearing on the row input conductors thereof during the presence of a write signal, to withhold the writing operation while the said binary signal is in a position in said shift register corresponding to a column which has already been written in and not erased, to mark a column as written in upon receipt of an off-mode binary signal from a column response conductor of said input matrix, to erase a column partially written in upon failure to receive said off-mode signal and to erase memories of all columns in turn when an erase signal and timing pulses are both present.

Claim 13

An adaptable associative electronic information storage system comprising: a. an input recognition matrix composed of a multiplicity of electrically identical memory and logic subcircuits connected in rows and columns; b. a multiplicity of input conductors each common to only one row of said subcircuits of said input matrix; c. a multiplicity of control conductors each common to only one column of said subcircuits of said input matrix, including for each column a column wriTe conductor, a column erase conductor and a column response conductor; d. an output selection matrix composed of a multiplicity of electrically identical memory and logic subcircuits connected in rows and columns; e. a multiplicity of conductors each common to only one row of said subcircuits of said output matrix including at least an output conductor for each of said rows; f. a multiplicity of control conductors each common to only one column of said subcircuits of said output matrix including at least a column activation conductor for each of said columns; g. an array of binary signal inverters each connected to respond to the condition of a column response conductor of said input matrix and to modify the operation of a column activation conductor of said output matrix; h. a timing pulse generator; i. system control means, including a switch arranged to command a training phase of the system, adapted during such training phase to impose a selected response pattern on said output conductors for writing into a column activated by its column activation conductor, to generate write or erase signals and to block the output of said timing pulse generator during erase signals so generated, said system control means also including a switch arranged to command generation of an erase signal without blocking of timing pulses; and j. a matrix control unit adapted to receive write and erase signals and timing pulses from said system control means, said matrix control unit comprising a linear array of logic and memory subcircuits and having a shift register adapted to advance a column scanning binary signal cyclically step by step through a series of memory cells each in a different one of said last-mentioned subcircuits in response to said timing pulses, said matrix control unit being so constituted as to be adapted to erase the memory of the column of said input matrix indicated by an off-mode signal of a column response conductor during the presence of an erase signal, to write into the memory of an empty column of said input matrix the signals appearing on the row input conductors thereof during the presence of a write signal, to withhold the writing operation while the said binary signal is in a position in said shift register corresponding to a column which has already been written in and not erased, to mark a column as written in upon receipt of an off-mode binary signal from a column response conductor of said input matrix, to erase a column partially written in upon failure to receive said off-mode signal and to erase memories of all columns in turn when an erase signal and timing pulses are both present.

Claim 14

An electronic information storage system as defined in claim 11 in which: k. said multiplicity of input conductors includes two input conductors common to each row of said subcircuits of said input matrix, of which one is directly connected to a binary signal input of the system and the other is connected to an inverting device so that its condition is the binary inverse of the condition of said binary signal conductors; l. each of said subcircuits of said input matrix contains two one bit memory elements, one of which is adapted to be set by one condition of a directly connected input conductor of its row and the other of which is adapted to be set by the same condition of the other input conductor of the said row.

Claim 15

An adaptable associative electronic information storage system comprising: a. an input recognition matrix composed of a multiplicity of electrically identical memory and logic subcircuits connected in rows and columns; b. a multiplicity of row input conductors each common to only one row of said subcircuits of said input matrix; c. an output selection matrix composed of a multiplicity of electrically identical memory and logic subcircuits connected in rows and columns; d. a multiplicity of row output conductors each common to only one row of said subcircuits of said output matrix; e. a mUltiplicity of control conductors each of which is common to only one column of said subcircuits of said input matrix and to only one column of said subcircuits of said output matrix, including for every column of said matrices a column write conductor and a column erase conductor; f. a multiplicity of column response conductors each common to only one column of said subcircuits of said input matrix; g. a multiplicity of column activation conductors each common to only one column of said subcircuits of said output matrix; h. an array of binary signal inverters each connected to respond to the condition of a column response conductor of said input matrix and to control the operation of a column activation conductor of said output matrix; i. a timing pulse generator; j. comparator means adapted for electrically representing a desired output response and for comparing said desired output response with the outputs of said output conductors, k. system control means, including a switch arranged to command a training phase of the system, adapted during such training phase to generate write or erase signals in response to conditions of said comparator means and to block the output of said timing pulse generator during erase signals so generated, said system control means also including a switch arranged to command generation of an erase signal without blocking of timing pulses, and l. a matrix control unit adapted to receive write and erase signals and timing pulses from said system control means said matrix control unit comprising a linear array of logic and memory subcircuits and having a shift register adapted to advance a column scanning binary signal cyclically step by step through a series of memory cells each in a different one of said last-mentioned subcircuits in response to said timing pulses, said matrix control unit being so constituted as to be adapted to erase the memory of the column of said input and output matrices indicated by an off-mode signal of a column response conductor in the presence of an erase signal, to write into the memory of an empty column of said matrices the signals appearing on the row input conductors of said input matrix and on the row output conductors of said output matrix during the presence of a write signal, to withhold the writing operation while the said scanning binary signal is in a position in said shift register corresponding to a column which has already been written in and not erased, to mark a column as written in upon receipt of an off-mode binary signal from a column response conductor of said input matrix, to erase a column partially written in upon failure to receive said off-mode signal and to erase memories of all columns in turn when an erase signal and timing pulses are both present.

Claim 16

An adaptable associative electronic information storage system comprising: a. an input recognition matrix composed of a multiplicity of electrically identical memory and logic subcircuits connected in rows and columns; b. a multiplicity of row input conductors each common to only one row of said subcircuits of said input matrix; c. an output selection matrix composed of a multiplicity of electrically identical memory and logic subcircuits connected in rows and columns; d. a multiplicity of row output conductors each common to only one row of said subcircuits of said output matrix; e. a mUltiplicity of control conductors each of which is common to only one column of said subcircuits of said input matrix and to only one column of said subcircuits of said output matrix, including for every column of said matrices a column write conductor and a column erase conductor; f. a multiplicity of column response conductors each common to only one column of said subcircuits of said input matrix; g. a multiplicity of column activation conductors each common to only one column of said subcircuits of said output matrix; h. an array of binary signal inverters each connected to respond to the condition of a column response conductor of said input matrix and to control the operation of a column activation conductor of said output matrix; i. a timing pulse generator; j. comparator means adapted for electrically representing a desired output response and for comparing said desired output response with the outputs of said output conductors, k. system control means, including a switch arranged to command a training phase of the system, adapted during such training phase to generate write or erase signals in response to conditions of said comparator means and to block the output of said timing pulse generator during erase signals so generated, said system control means also including a switch arranged to command generation of an erase signal without blocking of timing pulses, and l. a matrix control unit adapted to receive write and erase signals and timing pulses from said system control means said matrix control unit comprising a linear array of logic and memory subcircuits and having a shift register adapted to advance a column scanning binary signal cyclically step by step through a series of memory cells each in a different one of said last-mentioned subcircuits in response to said timing pulses, said matrix control unit being so constituted as to be adapted to erase the memory of the column of said input and output matrices indicated by an off-mode signal of a column response conductor in the presence of an erase signal, to write into the memory of an empty column of said matrices the signals appearing on the row input conductors of said input matrix and on the row output conductors of said output matrix during the presence of a write signal, to withhold the writing operation while the said scanning binary signal is in a position in said shift register corresponding to a column which has already been written in and not erased, to mark a column as written in upon receipt of an off-mode binary signal from a column response conductor of said input matrix, to erase a column partially written in upon failure to receive said off-mode signal and to erase memories of all columns in turn when an erase signal and timing pulses are both present.

Claim 17

An electronic information storage system as defined in claim 13 in which: m. said subcircuits of said input matrix contain at least one bit and no more than two bits of memory each, and n. said subcircuits of said output matrix contain one and only one bit of memory each.

Claim 18

An electronic information storage system as defined in claim 14 in which the memory content of each of said subcircuits, both of said input matrix and of said output matrix, are provided by bistable transistor circuits respectively forming part of said subcircuits.

Claim 19

An electronic information storage system as defined in claim 15 in which each of said subcircuits of said matrix control unit contain a one bit memory element adapted to indicate whether the corresponding column has been written in and not erased.

Claim 20

An electronic information storage system as defined in claim 16 in which each of said subcircuits of said matrix control unit also contains an additional one bit memory element adapted to be set by the activation of the corresponding column write conductor, to cause when set the blocking of a timing pulse from said shift register until the pattern, written into the column memory by said energization of said Column write conductor, has been removed.

Claim 21

An electronic information storage system as defined in claim 13 in each of the said subcircuits of said input matrix of which: o. there are three AND gates and a one bit memory element adapted (i) to be set by one AND gate having as inputs one of said row input conductors and one of said column write conductors (ii) to be reset by a column erase conductor and (iii) to provide a direct output and an inverse output respectively to the two other AND gates, the first-mentioned of which has for its only other input a connection of said row input conductor and the last-mentioned of which has for its only other input the inverse of the condition of said row input conductor, and p. an OR gate having two inputs, respectively connected to the outputs of said two last-mentioned AND gates, said OR gate having an inverted output connected to one of said column response conductors through a protective diode.

Claim 22

An electronic information storage system as defined in claim 13 in which each of said subcircuits of said output matrix contain two two-input AND gates and a one bit memory element adapted (i) to be set by one AND gate having an input connected to one of said column write conductors and its other input connected to one of said row output conductors, (ii) to be reset by one of said column erase conductors and (iii) to supply an output when set to the other of said AND gates, which has its other input connected to one of said column activation conductors and its output connected through a protective diode to said one of said row output conductors.

Claim 23

An electronic information storage system as defined in claim 13 in which: q. said multiplicity of input conductors includes two conductors common to each row of said subcircuits of said input matrix; r. each pair of input conductors common to the same row of subcircuits is provided with an entry circuit interconnecting it with a binary signal input conductor and with a ''''disregard'''' conductor the condition of which is adapted to indicate whether the subcircuits of a row are intended to disregard the condition of said binary input conductor, said entry means comprising a pair of AND gates both of which have an input activated by one and the same condition of said disregard conductor, one of which gates has another input which responds directly to the condition of said binary input conductor and defines the conductor connected to the gate output as the direct row input conductor and the other of which gates has another input that responds to the inverse of the condition of said binary input conductor and defines the conductor to which the gate output is connected as the inverse row input conductor, and s. each of said subcircuits of said input matrix contains two one bit memory elements, one of which is adapted to be set by one condition of said binary input conductor in the absence of a disregard signal and the other of which is adapted to be set by the other condition of said binary input conductor in the absence of a disregard signal.

Claim 24

An electronic information storage system as defined in claim 20 in which: t. the first-mentioned of said one bit memory elements in each of said subcircuits of said input matrix is associated (i) with an input AND gate by the output of which said memory element is adapted to be set, said input AND gate having inputs connected respectively to a direct row input conductor and a column write conductor and (ii) with an output AND gate with inputs connected respectively to the direct output (on-mode while set) of said first-mentioned memory element and to an inverse row input conductor for the same row served by said row input conductor, said output AND gate having its output connected through a protective diode to a column response conductor and u. the other of said one bit memory elements in each of said subcircuits of said input matrix is associated with (i) an input AND gate by the output of which said memory element is adapted to be set, said input AND gate having inputs connected respectively to said inverse row input conductor and to said column write conductor and (ii) with an output AND gate with inputs connected respectively to the direct output of said last-mentioned one bit memory elements and to said direct row input conductor, said output AND gate having its output connected through a protective diode to said column response conductor.

Claim 25

A system as defined in claim 1 in which each of said subcircuits in the input recognition matrix comprises: a pair of NOR gates, a one bit memory element and at least one NAND gate; said one NAND gate being responsive to signals on one of the row input conductors and on one of the column write conductors for setting the memory element in one state, the memory element being responsive to an inverted signal on one of the column erase conductors for setting it in the other state; one of the NOR gates being responsive to signals from said one of the row input conductors and from the memory element when in said other state; and the other of the NOR gates being responsive to inverted signals from said one of the row input conductors and from the memory element when in said one state, and each of said NOR gates having outputs coupled to one of the column control conductors through separate protective diodes for providing output signals thereto.

Claim 26

A system as defined in claim 22 in which the one bit memory element comprises: a pair of NAND gates each having a pair of inputs and an output, each output of one of said pair of NAND gates being connected to one of the pairs of inputs of the other of said pair of gates.

Claim 27

A system as defined in claim 1 in which each of the subcircuits in the output selection matrix comprises: a NOR gate, a one bit memory element and at least one NAND gate; said one NAND gate being responsive to signals on a set conductor and on one of the column write conductors for setting the memory element in one state, the memory element being responsive to an inverted signal on one of the column erase conductors for setting it in the other state; the NOR gate being responsive to a signal from the memory element when in said other state and to a signal from one of the column control conductors; and said NOR gate having an output coupled to one of the output conductors through a protective diode for providing output signals thereto.

Claim 28

A system as defined in claim 24 in which the one bit memory element comprises: a pair of NAND gates each having a pair of inputs and an output, each output of one of said pair of NAND gates being connected to one of the pairs of inputs of the other of said pair of gates.