Two-terminal transistor memory utilizing collector-base avalanche breakdown

Claim 2

A semiconductor memory cell comprising: a junction transistor having an uncontacted base, the potential of which floats at two values which represent, respectively, a ''''1'''' and ''''0'''' stored in the cell; first means coupled to the transistor for forward-biasing the emitter-base junction and biasing the collector-base junction to avalanche breakdown to set the potential of the base to a first value which is defined as a ''''1;'''' and second means coupled to the transistor for first increasing and then decreasing the potential of the collector such that the potential of the base is set to a second value which is defined as a ''''0,'''' and conduction occurs within the transistor if, and only if the base was initially at the ''''1'''' potential.

Claim 3

A semiconductor memory cell comprising: a junction transistor having an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to the collector of said transistor for first increasing the potential of the collector from an initial value to a value sufficient to bias the collector-base junction to avalanche breakdown and to increase the potential of the base sufficiently to forward-bias the emitter-base junction, thereby causing transistor conduction, and then decreasing the collector potential to its initial value, whereby transistor conduction is terminated, leaving holes trapped within the transistor for a period of time, whereupon the base potential starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; and a second circuit means coupled to the collector for first increasing the collector potential from an initial value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then decreasing the potential of the collector to its initial value, whereby the base potential assumes the ''''0'''' potential.

Claim 4

A semiconductor memory cell comprising: a junction transistor having an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to the collector of said transistor for first increasing the potential of the collector from an initial value to a value sufficient to bias the collector-base junction to avalanche breakdown and to increase the potential of the base sufficiently to forward-bias the emitter-base junction, thereby causing transistor conduction, and then decreasing the collector potential to its initial value, whereby transistor conduction is terminated, leaving holes trapped within the transistor for a period of time, whereupon the base potential starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; and a second circuit means coupled to the collector for first increasing the collector potential from an initial value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then decreasing the potential of the collector to its initial value, whereby the base potential assumes the ''''0'''' potential.

Claim 5

The memory cell of claim 2 wherein said first and second means constitute part of a voltage pulse circuit adapted to supply voltage pulses of different amplitudes.

Claim 6

The memory cell of claim 2 wherein the time required to decrease the collector potential from the value sufficient to bias the collector-base to avalanche breakdown to its initial value is lEss than or equal to the period of time in which the holes exist in said transistor after conduction is terminated.

Claim 7

The memory cell of claim 2 further comprising a conduction detector circuit coupled to the emitter of the transistor.

Claim 8

The memory cell of claim 5 wherein the conduction detector circuit is coupled to a reference potential.

Claim 9

The memory cell of claim 6 wherein said conduction detector circuit is a low impedance connecting said emitter to said reference potential.

Claim 10

Semiconductor memory apparatus comprising: a plurality of memory cells, each of which comprises an NPN junction transistor having an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to a preselected transistor cell for increasing the potential of the collector of said transistor from an initial value to a value sufficient to bias the collector-base junction to avalanche breakdown and to increase the potential of the base sufficiently to forward-bias the emitter-base junction, thereby causing transistor conduction, and then decreasing the potential of the collector to its initial value, whereby transistor conduction is terminated leaving holes trapped within the transistor for a period of time, whereupon the base starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; a second circuit means coupled to the collector of a preselected transistor memory cell for first increasing the collector potential from an initial value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then lowering the potential of the collector to its initial value, whereby the base potential assumes the ''''0'''' potential; and a third means forming a plurality of conduction paths coupling said memory cells to said first and second means.

Claim 11

Semiconductor memory apparatus comprising: a plurality of memory cells, each of which comprises an NPN junction transistor having an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to a preselected transistor cell for increasing the potential of the collector of said transistor from an initial value to a value sufficient to bias the collector-base junction to avalanche breakdown and to increase the potential of the base sufficiently to forward-bias the emitter-base junction, thereby causing transistor conduction, and then decreasing the potential of the collector to its initial value, whereby transistor conduction is terminated leaving holes trapped within the transistor for a period of time, whereupon the base starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; a second circuit means coupled to the collector of a preselected transistor memory cell for first increasing the collector potential from an initial value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then lowering the potential of the collector to its initial value, whereby the base potential assumes the ''''0'''' potential; and a third means forming a plurality of conduction paths coupling said memory cells to said first and second means.

Claim 12

The apparatus of claim 8 wherein said first and second circuit means constitute part of a voltage pulse circuit adapted to supply voltage pulses of different amplitudes and polarities.

Claim 13

The apparatus of claim 8 wherein the time required to decrease the collector potential from the value sufficient to bias the collector-base to avalanche breakdown to its initial value is less than or equal to the period of time in which the holes exist in said preselected transistor cell after conduction is terminated.

Claim 14

The semiconductor memory apparatus of claim 8 further comprising conduction detector circuits and wherein the plurality of conduction paths which couple the memory cells to the first and second means also couple the memory cells to the conduction detection circuits.

Claim 15

The apparatus of claim 11 wherein the conduction detector circuits are coupled to a reference potential.

Claim 16

The apparatus of claim 9 wherein said conduction detector circuits are low impedances coupling said second emitters to said reference potential.

Claim 17

The apparatus of claim 13 further comprising electrically activated switches which couple said conduction detector circuits to said emitters, whereby a ''''1'''' or ''''0'''' can be stored in or read out of any preselected memory cell without destroying the information stored in any of the other memory cells of said semiconductor memory apparatus.

Claim 18

Semiconductor memory apparatus comprising: a plurality of memory cells, each of which comprises a PNP junction transistor having an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to a preselected transistor cell for decreasing the potential of the collector of said transistor from an initial value to a value sufficient to bias the collector-base junction to avalanche breakdowN and to decrease the potential of the base sufficiently to forward-bias the emitter-base junction, thereby causing transistor conduction, and then increasing the potential of the collector to its initial value, whereby transistor conduction is terminated leaving electrons trapped within the transistor for a period of time, whereupon the base starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; a second circuit means coupled to the collector of a preselected transistor memory cell for first decreasing the collector potential from an initial value to a valve sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then increasing the potential of the collector to its initial value, whereby the base potential assumes the ''''0'''' potential; and a third means forming a plurality of conduction paths coupling said memory cells to said first and second means.

Claim 19

Semiconductor memory apparatus comprising: a plurality of memory cells, each of which comprises a PNP junction transistor having an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to a preselected transistor cell for decreasing the potential of the collector of said transistor from an initial value to a value sufficient to bias the collector-base junction to avalanche breakdowN and to decrease the potential of the base sufficiently to forward-bias the emitter-base junction, thereby causing transistor conduction, and then increasing the potential of the collector to its initial value, whereby transistor conduction is terminated leaving electrons trapped within the transistor for a period of time, whereupon the base starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; a second circuit means coupled to the collector of a preselected transistor memory cell for first decreasing the collector potential from an initial value to a valve sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then increasing the potential of the collector to its initial value, whereby the base potential assumes the ''''0'''' potential; and a third means forming a plurality of conduction paths coupling said memory cells to said first and second means.