US3699522A — Locomotive radio control system with address and …

Claim 1

Independent Claim 206 words

A communication system for controlling a remotely located device comprising; 1. a transmitter for sending time spaced signal pulses containing address and command instructions; 2. a receiver on the device responsive to the signal pulses adapted to provide a composite signal containing both the address and command instruction signals; 3. circuit means for detecting and determining the propriety of the command and address instruction signals from the composite signal, including a first timing circuit adapted to cause the circuit means to produce an output signal indicative of apparent proper command instruction signals after improper command instruction signals have been continuously received for a first predetermined interval encompassing more than a single signal pulse transmission; 4. gating means controlled by the circuit means for conducting the command instruction signals when the detection circuit indicates both proper command and address instructions; 5. a second timing circuit adapted to produce a predetermined command instruction after improper address instruction signals have been continuously received by the circuit means for a second predetermined interval longer than the first predetermined interval; and 6. application means responsive to the command instructions conducted by the gate circuit and produced by the second timing circuit for controlling the remotely located device in the desired manner.

Claim 2

Dependent Claim 206 words

A communication system for controlling a remotely located device comprising; 1. a transmitter for sending time spaced signal pulses containing address and command instructions; 2. a receiver on the device responsive to the signal pulses adapted to provide a composite signal containing both the address and command instruction signals; 3. circuit means for detecting and determining the propriety of the command and address instruction signals from the composite signal, including a first timing circuit adapted to cause the circuit means to produce an output signal indicative of apparent proper command instruction signals after improper command instruction signals have been continuously received for a first predetermined interval encompassing more than a single signal pulse transmission; 4. gating means controlled by the circuit means for conducting the command instruction signals when the detection circuit indicates both proper command and address instructions; 5. a second timing circuit adapted to produce a predetermined command instruction after improper address instruction signals have been continuously received by the circuit means for a second predetermined interval longer than the first predetermined interval; and 6. application means responsive to the command instructions conducted by the gate circuit and produced by the second timing circuit for controlling the remotely located device in the desired manner.

Claim 3

Dependent Claim 24 words

a receiver on the device responsive to the signal pulses adapted to provide a composite signal containing both the address and command instruction signals;

Claim 4

Dependent Claim 24 words

a receiver on the device responsive to the signal pulses adapted to provide a composite signal containing both the address and command instruction signals;

Claim 5

Dependent Claim 12 words

producing a composite signal containing both the address and command instruction signals,

Claim 6

Dependent Claim 12 words

producing a composite signal containing both the address and command instruction signals,

Claim 7

Dependent Claim 22 words

The system of claim 1 wherein the signal pulses comprise a radio carrier frequency wave modulated by address and command instruction signals.

Claim 8

Dependent Claim 64 words

circuit means for detecting and determining the propriety of the command and address instruction signals from the composite signal, including a first timing circuit adapted to cause the circuit means to produce an output signal indicative of apparent proper command instruction signals after improper command instruction signals have been continuously received for a first predetermined interval encompassing more than a single signal pulse transmission;

Claim 9

Dependent Claim 64 words

circuit means for detecting and determining the propriety of the command and address instruction signals from the composite signal, including a first timing circuit adapted to cause the circuit means to produce an output signal indicative of apparent proper command instruction signals after improper command instruction signals have been continuously received for a first predetermined interval encompassing more than a single signal pulse transmission;

Claim 10

Dependent Claim 35 words

a second timing circuit adapted to produce a predetermined command instruction after improper address instruction signals have been received by the circuit means for a second predetermined interval longer than the first predetermined interval; and

Claim 11

Dependent Claim 35 words

a second timing circuit adapted to produce a predetermined command instruction after improper address instruction signals have been received by the circuit means for a second predetermined interval longer than the first predetermined interval; and

Claim 12

Dependent Claim 21 words

The system of claim 2 wherein the address and command instruction signals take the form of a group of modulating frequencies.

Claim 13

Dependent Claim 15 words

separating the composite signal into command and address instruction signals, detecting each such signal, and

Claim 14

Dependent Claim 15 words

separating the composite signal into command and address instruction signals, detecting each such signal, and

Claim 15

Dependent Claim 64 words

circuit means for detecting and determining the propriety of the command and address instruction signals from the composite signal, including a first timing circuit adapted to cause the circuit means to produce an output signal indicative of apparent proper command instruction signals after improper command instruction signals have been continuously received for a first predetermined interval encompassing more than a single signal pulse transmission;

Claim 16

Dependent Claim 64 words

circuit means for detecting and determining the propriety of the command and address instruction signals from the composite signal, including a first timing circuit adapted to cause the circuit means to produce an output signal indicative of apparent proper command instruction signals after improper command instruction signals have been continuously received for a first predetermined interval encompassing more than a single signal pulse transmission;

Claim 17

Dependent Claim 24 words

gating means controlled by the circuit means for conducting the command instruction signals when the detection circuit indicates both proper command and address instructions;

Claim 18

Dependent Claim 24 words

gating means controlled by the circuit means for conducting the command instruction signals when the detection circuit indicates both proper command and address instructions;

Claim 19

Dependent Claim 21 words

checking the propriety of the instruction signals, and if both are proper operating the vehicle in accordance with the command instructions,

Claim 20

Dependent Claim 21 words

checking the propriety of the instruction signals, and if both are proper operating the vehicle in accordance with the command instructions,

Claim 21

Dependent Claim 32 words

The system of claim 3 wherein the carrier frequency wave is frequency modulated by the address and command instruction signals which are in the form of a distinctive group of modulating frequencies.

Claim 22

Dependent Claim 24 words

a gating means controlled by the circuit means for conducting the command instruction when the detection circuit indicates both proper command and address instructions.

Claim 23

Dependent Claim 24 words

a gating means controlled by the circuit means for conducting the command instruction when the detection circuit indicates both proper command and address instructions.

Claim 24

Dependent Claim 50 words

The system of claim 4 wherein the circuit means includes filters for recovering the command instruction signals from the composite signal, a circuit for detecting the command instruction signals, and a logic circuit responsive to the detected signals adapted to produce an output signal indicative of improper command instruction signals.

Claim 25

Dependent Claim 15 words

upon receipt of improper instruction signals preventing any new command instruction from operating the device,

Claim 26

Dependent Claim 15 words

upon receipt of improper instruction signals preventing any new command instruction from operating the device,

Claim 27

Dependent Claim 36 words

a second timing circuit adapted to produce a predetermined command instruction after improper address instruction signals have been continuously received by the circuit means for a second predetermined interval longer than the first predetermined interval; and

Claim 28

Dependent Claim 36 words

a second timing circuit adapted to produce a predetermined command instruction after improper address instruction signals have been continuously received by the circuit means for a second predetermined interval longer than the first predetermined interval; and

Claim 29

Dependent Claim 29 words

application means responsive to the command instructions conducted by the gate circuit and produced by the second timing circuit for controlling the remotely located device in the desired manner.

Claim 30

Dependent Claim 29 words

application means responsive to the command instructions conducted by the gate circuit and produced by the second timing circuit for controlling the remotely located device in the desired manner.

Claim 31

Dependent Claim 30 words

upon improper command instruction signals continuously persisting for longer than a first predetermined interval allowing new command instructions to operate the device provided the address instruction signals are proper, and

Claim 32

Dependent Claim 30 words

upon improper command instruction signals continuously persisting for longer than a first predetermined interval allowing new command instructions to operate the device provided the address instruction signals are proper, and

Claim 33

Dependent Claim 101 words

The system of claim 5 wherein the first timing circuit comprises, an impedance network having a desired discharge time constant, the network being charged by correct detected address instruction signals except when improper command instruction signals are received which cause the network to discharge, a switching circuit sensitive to the voltage level on the network for effecting an indication of apparent proper command instruction signals from the circuit means whenever improper command instruction signals have been continuously detected for the first predetermined interval sufficient to discHarge the voltage level on the network below a selected value thereby actuating the switching circuit.

Claim 34

Dependent Claim 130 words

The system of claim 6 wherein the first timing circuit comprises a resistor capacitor network having a desired discharge time constant, the network being charged by correct detected address instruction signals except when the logic circuit produces an output signal indicative of an improper command instruction which logic output signal clamps the circuit means output signal and the input to the network to a potential value causing the network to discharge, a transistor switching circuit responsive to the voltage level on the network which changes output conductance state whenever the voltage level falls below a selected value, and a relay controlled by the change of conductance in the transistor switching circuit to remove the logic output signal from the circuit means output signal thereby indicating apparent proper command instruction signals.

Claim 35

Dependent Claim 29 words

upon receipt of improper address instruction signals persisting for longer than a second predetermined interval greater than the first predetermined interval then imposing a selected command on the device.

Claim 36

Dependent Claim 29 words

upon receipt of improper address instruction signals persisting for longer than a second predetermined interval greater than the first predetermined interval then imposing a selected command on the device.

Claim 37

Dependent Claim 114 words

The system of claim 6 in which the command instruction signals comprise a group of modulating frequencies representing a complete instruction word, each digit of the instruction word being indicated by one of two possible frequencies, wherein the logic circuit comprises a resistor summing network having inputs from the filters associated with each possible frequency representing an instruction digit, a bridge circuit responsive to the summing network adapted to produce an output signal indicative of the propriety of the command digit, and a transistor switching circuit responsive to the bridge output for producing a particular output voltage indicative of an improper command instruction whenever the bridge circuit output signal indicates an improper command digit.

Claim 38

Dependent Claim 46 words

The system of claim 8 wherein the bridge circuit comprises a diode-resistor network having the output taken across the junctions of the diode and resistor pairs, the input connected to the junction of the diodes and a reference potential connected to the junction of the resistors.

Claim 39

Dependent Claim 42 words

The system of claim 8 wherein the application circuit is programmed to produce a shutdown stop of the device whenever an improper command instruction signal is conducted to the application circuit or whenever the second timing circuit produces the predetermined command instruction.

Claim 40

Dependent Claim 21 words

The system of claim 10 wherein the application circuit comprises relays for initiating commands to the functional controls of the device.

Claim 41

Dependent Claim 23 words

A receiver for producing command instruction signals to control a device in accordance with transmitted signal pulses containing address and command instructions comprising:

Claim 42

Dependent Claim 23 words

A receiver for producing command instruction signals to control a device in accordance with transmitted signal pulses containing address and command instructions comprising:

Claim 43

Dependent Claim 37 words

The radio receiver of claim 12 wherein the transmitted signal pulses comprise a carrier frequency which is frequency modulated by address and/or command instruction signals which are in the form of a distinctive group of modulating frequencies.

Claim 44

Dependent Claim 50 words

The receiver of claim 13 whereIn the circuit means includes filters for recovering the command instruction signals from the composite signal, a circuit for detecting the command instruction signals, and a logic circuit responsive to the detected signals adapted to produce an output signal indicative of improper command instruction signals.

Claim 45

Dependent Claim 130 words

The receiver of claim 14 wherein the first timing circuit comprises, a resistor capacitor network having a desired discharge time constant, the network being charged by correct detected address instruction signals except when the logic circuit produces an output signal indicative of an improper command instruction, which logic output signal clamps the circuit means output signal and the input to the network to a potential value causing the network to discharge, a transistor switching circuit responsive to the voltage level on the network which changes output conductance state whenever the voltage level falls below a selected value, and a relay controlled by the change of conductance in the transistor switching circuit to remove the logic output signal from the circuit means output signal thereby indicating apparent proper command instruction signals.

Claim 46

Dependent Claim 114 words

The receiver of claim 15 in which the command instruction signals comprise a group of modulating frequencies representing a complete instruction word, each digit of the instruction word being indicated by one of two possible frequencies, wherein the logic circuit comprises a resistor summing network having inputs from the filters associated with each possible frequency representing an instruction digit, a bridge circuit responsive to the summing network adapted to produce an output signal indicative of the propriety of the command digit, and a transistor switching circuit responsive to the bridge output for producing a particular output voltage indicative of an improper command instruction whenever the bridge circuit output signal indicates an improper command digit.

Claim 47

Independent Claim 33 words

A method for imposing command instructions on a remotely located device wherein radio signal pulses containing address and command instruction signals are transmitted to a receiver on the device, comprising the steps of:

Claim 48

Independent Claim 33 words

A method for imposing command instructions on a remotely located device wherein radio signal pulses containing address and command instruction signals are transmitted to a receiver on the device, comprising the steps of:

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1975-10-17	1976-04-17	1976-10-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1979-10-17	1980-04-17	1980-10-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1983-10-17	1984-04-17	1984-10-17	$7700.00	Window Closed / Lapsed

Locomotive radio control system with address and command signals

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