US3698012A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-character electronic display
Assignee: Texas Instruments Inc
•
Filing: 1968-12-31
•
Granted: 1972-10-10
•
Expires: 1988-12-31
Abstract
Abstract Disclosed are multiple character electronic display devices utilizing plurality of character matrices, each of which includes plurality of thermally isolated semiconductor mesas which are heated by current passed through a resistance. The current in each mesa is controlled by a transistor formed therein, and such transistors may have a common collector voltage and a common emitter voltage supply lead which may be individually closed by a switch to enable a desired character. The bases of the transistors of corresponding mesas in all of the character matrices may be connected to common control lines so that all character matrices may be controlled by the same character generator. A particular diffusion pattern for the individual elements of the matrices is also disclosed which utilizes an extended collector transistor having a longitudinally extending, double diffused tunnel to provide cross connections from the control lines to the base contacts of the elements of an array.
Inventors
- 👤 Clifford H Ensminger
- 👤 Edward M Ruggiero
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:35
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/04; G09G3/16; B; B41; B41J; B41J2/00; B41J2/315; B41J2/32; B41J2/35; B41J2/355
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
122 words
In an electronic display, the combination comprising: a plurality of character matrices with each matrix having rows and columns of a corresponding number of semiconductor elements each including a transistor and a resistance, means for electrically interconnecting the collectors of each transistor in each matrix through its respective resistance, means electrically interconnecting the emitters of each transistor of each matrix, means for selectively sequentially enabling said matrices, and separate control lines respectively common to the bases of the transistors of said rows of corresponding ones of said semiconductor elements in said matrices, wherein the collectorbase junctions of the transistors connected to the unactivated control lines in a disabled matrix are reversed biased and block current that may return to the enabled matrix.
Claim 2
Dependent Claim
122 words
In an electronic display, the combination comprising: a plurality of character matrices with each matrix having rows and columns of a corresponding number of semiconductor elements each including a transistor and a resistance, means for electrically interconnecting the collectors of each transistor in each matrix through its respective resistance, means electrically interconnecting the emitters of each transistor of each matrix, means for selectively sequentially enabling said matrices, and separate control lines respectively common to the bases of the transistors of said rows of corresponding ones of said semiconductor elements in said matrices, wherein the collectorbase junctions of the transistors connected to the unactivated control lines in a disabled matrix are reversed biased and block current that may return to the enabled matrix.
Claim 3
Dependent Claim
48 words
The combination of claim 1 wherein: said means for electrically interconnecting the collectors electrically interconnects all the collectors of each transistor of all of said matrices, and said means for selectively sequentially enabling said matrices selectively electrically connects the emitters of each transistor of each matrix to ground.
Claim 4
Dependent Claim
50 words
The combination of claim 1 wherein: said means for electrically interconnecting the emitters electrically interconnects all the emitters of each transistor of all of said matrices, and said means for selectively sequentially enabling said matrices selectively electrically connects the collectors of each transistor in each matrix to a voltage supply.
Claim 5
Dependent Claim
114 words
In an electronic display, the combination comprising: a row of semiconductor elements each including a transistor and a resistance, means for electrically interconnecting the collectors of a first and another second group of the collectors of each transistor in each of said groups through its respective resistance, means for electrically interconnecting the emitters of each transistor of each group, means for selectively sequentially enabling said groups and separate control lines respectively common to different bases of the transistors in different ones on said groups wherein the collector-base junctions of the transistors connected to the unactivated control lines in a disabled group are reverse biased and block current that may return to the enabled group.
Claim 6
Dependent Claim
114 words
In an electronic display, the combination comprising: a row of semiconductor elements each including a transistor and a resistance, means for electrically interconnecting the collectors of a first and another second group of the collectors of each transistor in each of said groups through its respective resistance, means for electrically interconnecting the emitters of each transistor of each group, means for selectively sequentially enabling said groups and separate control lines respectively common to different bases of the transistors in different ones on said groups wherein the collector-base junctions of the transistors connected to the unactivated control lines in a disabled group are reverse biased and block current that may return to the enabled group.
Claim 7
Dependent Claim
48 words
The combination of claim 4 wherein: said means for electrically interconnecting the collectors electrically interconnects all the collectors of each transistor of all of said matrices, and said means for selectively sequentially enabling said groups selectively electrically connects the emitters of each transistor of each group to ground.
Claim 8
Dependent Claim
50 words
The combination of claim 4 wherein: said means for electrically interconnecting the emitters electrically interconnects all the emitters of each transistor of all of said groups, and said means for selectively sequentially enabling said groups selectively electrically connects the collectors of each transistor in each group to a voltage supply.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-10 | 1976-04-10 | 1976-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-10 | 1980-04-10 | 1980-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-10 | 1984-04-10 | 1984-10-10 | $7700.00 | Window Closed / Lapsed |