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US3697980A Expired / Lapsed US ⏱️ 0.0 years remaining

Isolated digital-to-analog converter

Assignee: International Business Machines Corp
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Filing: 1971-06-30
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Granted: 1972-10-10
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Expires: 1991-06-30
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Abstract

Abstract A digital-to-analog converter employing a pair of operational amplifiers connected in a balanced differential configuration to supply an analog output to a two-terminal load. The data and power inputs are isolated from the converter by isolation couplers. Each bit of binary data is sensed at the summing junction of each amplifier by means of a pair of balanced resistors which are switched in accordance with the binary signal. Each set of balanced resistors so sensed is in parallel with the other sets between the summing junctions. The balanced differential configuration enables either terminal at the twoterminal load to be at ground reference potential without deteriorating the common-mode rejection capability of the circuit, thereby eliminating the effect of voltages existing between the ground reference at the load and the ground reference at the binary and power input terminals of the converter.

Inventors

  • 👤 Stavros Boinodiris
  • 👤 George A Hellwarth

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 00:14
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 218 words
A highly isolated digital-to-analog converter for converting data received at a plurality of digital input terminals to an analog output signal comprising: AC data isolation coupling means for coupling the digital input signals into the converter; first and second differential amplifier means arranged in a balanced differential configuration each including an input summing junction, an input reference terminal and an output terminal, for generating an analog signal across said output terminals; a plurality of switching stages, each stage coupled to an associated digital input terminal by said isolation coupling means, and including a balanced pair of transistor switching devices and a balanced pair of resistive elements, each said stage arranged to be coupled between the summing junctions of said first and second amplifier means in response to a digital signal at its associated input terminal; an output load having a first terminal and a reference terminal; high-frequency impedance means coupling the output terminals of said amplifiers with the first and reference terminals of the output load for preventing high frequency input leakage current from flowing through the load; said balanced differential configuration preventing common-mode voltages from inducing differential voltages across the load, whereby either output terminal of said amplifiers may be connected to the reference terminal of the load without affecting the common-mode rejection response of the converter.
Claim 2
Dependent Claim 218 words
A highly isolated digital-to-analog converter for converting data received at a plurality of digital input terminals to an analog output signal comprising: AC data isolation coupling means for coupling the digital input signals into the converter; first and second differential amplifier means arranged in a balanced differential configuration each including an input summing junction, an input reference terminal and an output terminal, for generating an analog signal across said output terminals; a plurality of switching stages, each stage coupled to an associated digital input terminal by said isolation coupling means, and including a balanced pair of transistor switching devices and a balanced pair of resistive elements, each said stage arranged to be coupled between the summing junctions of said first and second amplifier means in response to a digital signal at its associated input terminal; an output load having a first terminal and a reference terminal; high-frequency impedance means coupling the output terminals of said amplifiers with the first and reference terminals of the output load for preventing high frequency input leakage current from flowing through the load; said balanced differential configuration preventing common-mode voltages from inducing differential voltages across the load, whereby either output terminal of said amplifiers may be connected to the reference terminal of the load without affecting the common-mode rejection response of the converter.
Claim 3
Dependent Claim 45 words
A digital-to-analog converter as in claim 1 wherein said high frequency impedance means is a balun and said AC isolation coupling means comprises an iron-core transformer having means for shielding said transformer from common-mode signals emanating from the converter reference or the output load reference.
Claim 4
Dependent Claim 37 words
A digital-to-analog converter as in claim 1 wherein the resistance of said balanced resistors in each said switching stage is in geometric progression with respect to the resistance of said balanced resistors in the preceding switching stage.
Claim 5
Dependent Claim 49 words
A digital-to-analog converter as in claim 1 wherein each said differential amplifier means comprises an operational amplifier having feedback means connected between the output terminal and the summing junction, said summing junctions and said balanced resistors coupled between the summing junctions being supplied by a source of bias current.
Claim 6
Dependent Claim 45 words
A digital-to-analog converter as in claim 4 wherein said source of bias current comprises: a source of input power; reference voltage means for providing said bias current; and AC power isolation coupling means for coupling the source of input power to the reference voltage means.
Claim 7
Dependent Claim 44 words
A digital-to-analog converter as in claim 5 further comprising: capacitance means connected between said AC power isolation coupling means and the high frequency impedance means for bypassing around the differential amplifier means any high frequency currents generated across said AC power isolation coupling means.
Claim 8
Dependent Claim 34 words
A digital-to-analog converter as in claim 1 wherein said transistor devices are complementary conductivity types driven in the inverted mode between said resistive pair, thereby driving the balanced resistors with equal and balanced impedances.
Claim 9
Dependent Claim 43 words
A digital-to-analog converter as in claim 7 further comprising: capacitance means connected between the collectors of said transistors and the high frequency impedance means for bypassing around the differential amplifier means any high frequency currents generated across the AC data isolation coupling means.
Claim 10
Independent Claim 312 words
A system for converting digital data into an analog voltage form comprising: a plurality of digital input terminals; switching means including first and second complementary conductivity type transistors driven in the inverted mode, one said switching means associated with each input terminal; AC data isolation means including shielded transformers coupled to each input terminal for operating said switching means in accordancE with signals on their associated input terminals; first and second operational amplifiers arranged in a balanced differential configuration, each including an input summing junction, an input reference terminal and an output terminal, for generating an analog signal across said output terminals; an output load having a first terminal and a reference terminal; high-frequency impedance means including a balun coupling the output terminals of said amplifiers with the first and reference terminals of the output load for preventing high frequency input leakage current from flowing through the load; a source of input AC power; AC power isolation means including a shielded transformer for coupling the power source to the input of a reference voltage source, said reference source supplying bias potentials to the reference input terminals of said amplifiers and bias current to the summing junctions of said amplifiers; a set of first and second balanced resistors associated with each digital input terminal and coupled between said first and second operational amplifiers, respectively, and the output of said first and second transistors, respectively, said first and second resistors connected in series relationship with each other between the summing junctions of said amplifiers when said transistors are operated and in parallel with the so-connected sets of resistors associated with other digital input terminals; said balanced differential configuration preventing common-mode voltages from inducing differential voltages across the load, whereby either output terminal of said amplifiers may be connected to the reference terminal of the load without affecting the common-mode rejection response of the converter.
Claim 11
Independent Claim 312 words
A system for converting digital data into an analog voltage form comprising: a plurality of digital input terminals; switching means including first and second complementary conductivity type transistors driven in the inverted mode, one said switching means associated with each input terminal; AC data isolation means including shielded transformers coupled to each input terminal for operating said switching means in accordancE with signals on their associated input terminals; first and second operational amplifiers arranged in a balanced differential configuration, each including an input summing junction, an input reference terminal and an output terminal, for generating an analog signal across said output terminals; an output load having a first terminal and a reference terminal; high-frequency impedance means including a balun coupling the output terminals of said amplifiers with the first and reference terminals of the output load for preventing high frequency input leakage current from flowing through the load; a source of input AC power; AC power isolation means including a shielded transformer for coupling the power source to the input of a reference voltage source, said reference source supplying bias potentials to the reference input terminals of said amplifiers and bias current to the summing junctions of said amplifiers; a set of first and second balanced resistors associated with each digital input terminal and coupled between said first and second operational amplifiers, respectively, and the output of said first and second transistors, respectively, said first and second resistors connected in series relationship with each other between the summing junctions of said amplifiers when said transistors are operated and in parallel with the so-connected sets of resistors associated with other digital input terminals; said balanced differential configuration preventing common-mode voltages from inducing differential voltages across the load, whereby either output terminal of said amplifiers may be connected to the reference terminal of the load without affecting the common-mode rejection response of the converter.
Claim 12
Dependent Claim 102 words
A system as in claim 9 wherein the total resistance of said balanced resistors associated with a digital input terminal is in geometric progression with respect to the total resistance of said balanced resistors associated with the preceding digital input terminal, and further comprising: capacitance means connected between the collectors of said transistors and the balun for bypassing around the operational amplifiers any high frequency currents generated across the AC input transformers; and capacitance means connected between said AC power isolation transformer and the balun for bypassing around the operational amplifiers any high frequency currents generated across said AC power isolation transformers.

References Cited (Backward Citations)

US3223992A Cited
US3426345A Cited
US3449741A Cited
US3543264A Cited
US3588880A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-10-10 1976-04-10 1976-10-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-10-10 1980-04-10 1980-10-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-10-10 1984-04-10 1984-10-10 $7700.00 Window Closed / Lapsed

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