US3697884A
Expired / Lapsed
US
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Synchronizing a phase-locked-loop from phase encoded signals
Assignee: Telex Computer Products Inc
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Filing: 1971-07-16
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Granted: 1972-10-10
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Expires: 1991-07-16
Abstract
Abstract In this invention a voltage controlled oscillator provides an output signal which is a clock signal. This is synchronized with the incoming phase-encoded (PE) signal through a phase detector in a phase-locked-loop (PLL). To synchronize the clock signal to the PE signal both signals must be negative-going and positivegoing at the same time. This invention corrects the PE signal to a synchronizing signal, by use of an inverting element, whenever the PE signal and clock are not changing in the same direction. A NAND gate connected to the synchronizing signal and the clock senses differences and controls a flip-flop, which inverts the PE signal.
Inventors
- 👤 Larry W Fort
- 👤 Connie T Marshall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:29
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0807
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
104 words
In an apparatus for synchronizing a clock signal to a phaseencoded (PE) signal, which apparatus includes a phase-locked-loop (PLL) sensitive to negative-going signals, and in which said PLL receives on a first input terminal a synchronizing signal which is a function of said PE signal, and receives on a second input terminal its own output, defined as a clock signal, the improvement, comprising: a. first means for detecting differences in potential level between said PE signal and said clock signal; and b. second means responsive to said first means for inverting said PE signal, the output of said second means comprising said synchronizing signal.
Claim 2
Dependent Claim
104 words
In an apparatus for synchronizing a clock signal to a phaseencoded (PE) signal, which apparatus includes a phase-locked-loop (PLL) sensitive to negative-going signals, and in which said PLL receives on a first input terminal a synchronizing signal which is a function of said PE signal, and receives on a second input terminal its own output, defined as a clock signal, the improvement, comprising: a. first means for detecting differences in potential level between said PE signal and said clock signal; and b. second means responsive to said first means for inverting said PE signal, the output of said second means comprising said synchronizing signal.
Claim 3
Dependent Claim
30 words
The apparatus of claim 1 in which said first means comprises a NAND gate with one input being the inverted synchronizing signal, and the second input being the clock signal.
Claim 4
Dependent Claim
20 words
The apparatus of claim 1 in which said second means comprises a two position flip-flop controlling an exclusive OR gate.
References Cited (Backward Citations)
US3602834A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-10 | 1976-04-10 | 1976-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-10 | 1980-04-10 | 1980-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-10 | 1984-04-10 | 1984-10-10 | $7700.00 | Window Closed / Lapsed |