Synchronous am detector

Claim 2

An integrated detector circuit for detecting amplitude modulated input signals of a predetermined frequency, including in combination: multiplier circuit means including transistor differential amplifier switch means having a switching input, first and second outputs, and a signal input; means for applying the modulated input signals to the signal input of the differential amplifier switch means; limiter circuit means; means for applying the modulated input signals to the limiter circuit means to drive the limiter circuit means to limiting to produce an output signal at said predetermined frequency without said amplitude modulation; frequency selective filter means coupled to the limiter circuit means and tuned to said predetermined frequency for attenuating signals at frequencies other than said predetermined frequency; and the output of the limiter circuit means being coupled with the switching input of the transistor differential amplifier switch means, causing the differential amplifier switch means to alternately switch input signals applied to the signal input thereof between the first and second outputs at said predetermined frequency so that detected amplitude modulated signals appear at the outputs of the multiplier circuit means.

Claim 3

The combination according to claim 1 further including output load impedance means coupled with the outputs of the differential amplifier switch means, the value of the load impedance means selected for interaction with the inherent circuit capacitances of the differential amplifier switch means to roll-off the detector frequency response at frequencies above said predetermined frequency.

Claim 4

A wide-band fully balanced AM detector circuit for detecting the amplitude modulation of a carrier signal forming part of a composite signal having at least another signal side band subcarrier signal, the side bands of which may produce a beat signal in a frequency range which interferes with the detected signal, said detector circuit including in combination: first, second, third and fourth transistor differential amplifiers, each including a pair of transistors having base, collector and emitter electrodes, the emitter electrodes of each pair being coupled in common; means for coupling the collectors of the transistors of the third differential amplifier to the common coupled emitters of the first and second differential amplifiers, respectively, to form a doubly balanced synchronous detector circuit; means for applying the composite signal to be demodulated to the bases of the transistors of the third differential amplifier; means for applying the composite signal to the bases of the transistors of the fourth differential amplifier, with the magnitude of the input signals applied to the fourth differential amplifier being sufficient to drive the transistors thereof between saturation and cut-off to produce on the collectors thereof an amplitude limited signal at the carrier signal frequency; means for coupling the collectors of the transistors of the fourth differential amplifier to the bases of respective ones of each of the transistors in the first and second differential amplifiers to alternately switch the transistors in the first and second differential amplifiers betWeen conduction and non-conduction on alternate half cycles of the carrier signal; and frequency selective circuit means coupled with the collectors of the transistors of the fourth differential amplifier and tuned to the carrier frequency for reducing unwanted beat signals.

Claim 5

A wide-band fully balanced AM detector circuit for detecting the amplitude modulation of a carrier signal forming part of a composite signal having at least another signal side band subcarrier signal, the side bands of which may produce a beat signal in a frequency range which interferes with the detected signal, said detector circuit including in combination: first, second, third and fourth transistor differential amplifiers, each including a pair of transistors having base, collector and emitter electrodes, the emitter electrodes of each pair being coupled in common; means for coupling the collectors of the transistors of the third differential amplifier to the common coupled emitters of the first and second differential amplifiers, respectively, to form a doubly balanced synchronous detector circuit; means for applying the composite signal to be demodulated to the bases of the transistors of the third differential amplifier; means for applying the composite signal to the bases of the transistors of the fourth differential amplifier, with the magnitude of the input signals applied to the fourth differential amplifier being sufficient to drive the transistors thereof between saturation and cut-off to produce on the collectors thereof an amplitude limited signal at the carrier signal frequency; means for coupling the collectors of the transistors of the fourth differential amplifier to the bases of respective ones of each of the transistors in the first and second differential amplifiers to alternately switch the transistors in the first and second differential amplifiers betWeen conduction and non-conduction on alternate half cycles of the carrier signal; and frequency selective circuit means coupled with the collectors of the transistors of the fourth differential amplifier and tuned to the carrier frequency for reducing unwanted beat signals.

Claim 6

The combination according to claim 3 wherein the frequency selective circuit means includes first circuit means having a peak frequency response at the carrier frequency and second circuit means forming a notch at the frequency of said subcarrier signal.

Claim 7

The combination according to claim 4 wherein the first circuit of the frequency selective circuit means is a parallel resonant circuit, resonant at the carrier frequency, and the second circuit for forming the notch is a series resonant circuit, resonant at said subcarrier frequency.

Claim 8

The combination according to claim 3 wherein the composite signal includes an amplitude modulated video carrier, the amplitude modulation of which the detector circuit is designed to detect, a chroma subcarrier signal and a sound subcarrier signal, with the chroma and sound subcarrier signals having side bands which interact to produce a beat frequency which is within the video band width, with the frequency selective circuit means being tuned to the video carrier frequency to thereby attenuate the chroma and sound subcarrier signals in the switching signals applied to the bases of the transistors of the first and second differential amplifiers.

Claim 9

The combination according to claim 6 further including output load resistance means coupled with the collectors of the transistors of the first and second differential amplifiers, the value of the load resistance means being such that a roll-off filter is formed by the load resistance means and the inherent collector capacitances of the first and second differential amplifier transistors for rolling off the detector frequency response at frequencies above the bandwidth of said video carrier signal.

Claim 10

The combination according to claim 3 wherein at least said first, second, third and fourth differential amplifiers all are formed as part of a single integrated circuit thereby to substantially match the characteristics of operation of said differential amplifiers.

Claim 11

The combination according to claim 8 wherein the collectors of transistors of the first and second differential amplifiers are cross-coupled to provide an output signal indicative of the amplitude modulation of the carrier signal.

Claim 12

The combination according to claim 3 further including first and second oppositely poled hot-carrier diodes coupled in parallel across the collectors of the transistors of the fourth differential amplifier.