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US3696349A Expired / Lapsed US ⏱️ 0.0 years remaining

Block organized random access memory

Assignee: Unisys Corp
•
Filing: 1971-06-04
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Granted: 1972-10-03
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Expires: 1991-06-04
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Abstract

Abstract A three-dimensional magnetizable memory stack of Mated-Film memory elements each of which provides a substantially closed flux path, except for a gap transverse to the element''s easy axis, is disclosed. The stack is comprised of a plurality of superposed, i.e., laid one upon the other so as to make all likeoriented-parts vertically coincide, similar transfer arrays sandwiched between a write array and a read array, all arrays having similarly arranged Mated-Film write/read, transfer memory elements with a gap in the top layer for providing an external longitudinal steering field + OR - HL across the gap that is inductively coupled to each next superposed memory element. Information is written into the memory elements of the write array using word-organized coincident currents. Information from each memory element is then transferred vertically through the stack in successive transfer operations between each next superposed memory element by using the steering field + OR - HL of the next bottom memory element in coincidence with an applied transverse DC drive field HT at the next top memory element. The information written in the bottom write array is successively transferred or shifted from transfer array to transfer array and into the top read array from which it is read out in a wordorganized random-access manner.

Inventors

  • 👤 Alan D Kaske
  • 👤 Gerald F Sauter

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 12:44
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/02; G11C19/08; G11C19/0875

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 151 words
A memory stack, comprising: a plurality of two-dimensional memory planes, each of said memory planes compRising an array of similarly oriented magnetizable memory elements with each of said memory elements having a similarly oriented gap in its otherwise substantially closed flux path for providing an external steering field + OR - HL that is oriented across the gap and along the substantially closed flux path aligned easy axis, the polarity of said steering field + OR - HL indicating the particular binary data state that is stored in the bit-defining memory element; said memory planes being oriented into a superposed memory stack with the corresponding similarly oriented memory elements of each of said memory planes being aligned in a superposed configuration with their respective gaps being similarly superposed for inductively coupling the steering field of the next bottom superposed memory element into the gap of the next top superposed memory element.
Claim 2
Dependent Claim 151 words
A memory stack, comprising: a plurality of two-dimensional memory planes, each of said memory planes compRising an array of similarly oriented magnetizable memory elements with each of said memory elements having a similarly oriented gap in its otherwise substantially closed flux path for providing an external steering field + OR - HL that is oriented across the gap and along the substantially closed flux path aligned easy axis, the polarity of said steering field + OR - HL indicating the particular binary data state that is stored in the bit-defining memory element; said memory planes being oriented into a superposed memory stack with the corresponding similarly oriented memory elements of each of said memory planes being aligned in a superposed configuration with their respective gaps being similarly superposed for inductively coupling the steering field of the next bottom superposed memory element into the gap of the next top superposed memory element.
Claim 3
Dependent Claim 132 words
The memory stack of claim 1 wherein the bottom and top memory planes are write and read arrays, respectively, and the intermediate memory planes sandwiched therebetween are transfer arrays; and wherein said write and read arrays are substantially similar including a parallel set of word lines and an orthogonally oriented parallel set of bit/sense lines with a memory element oriented at each word line, bit/sense line intersection for defining a multibit word along each word line; said transfer arrays include a parallel set of word lines with a plurality of memory elements oriented along each word line for defining a multibit word along each word line; the next superposed bit defining memory elements of the superposed word lines of said write, transfer and read arrays inductively intercoupled by their respective steering fields.
Claim 4
Dependent Claim 107 words
The memory stack of claim 2 further including: word drive means selectively coupled to the word lines of said write array for coupling a word drive field HT to a selected one of said word lines of said write array; bit drive means selectively coupled to the bit lines of said write array for coupling a bit drive field + or - HL to all the bit lines associated with said one selected word line; said word drive field HT and said bit drive fields + or - HL coincidentally setting the magnetization of the coincidentally affected bit defining memory elements into a selected one binary state.
Claim 5
Dependent Claim 73 words
The memory stack of claim 3 further including: word drive means selectively coupled to the word lines of said transfer arrays and coupling a word drive field HT to selected superposed word lines of said transfer arrays for successively transferring the multibit word stored along a selected word line in said write array bit-parallel through the superposed word lines of said transfer arrays into the superposed word line of the top transfer array.
Claim 6
Dependent Claim 100 words
The memory stack of claim 4 further including: word drive means selectively coupled to the word lines of said read array and coupling a word drive field HT to a selected one of said word lines of said read array for transferring the multibit word stored along a word line of said top transfer array into the superposed word line of said read array and subsequently reading out the multibit word transferred into said word line of said read array along the bit lines associated with the bit defining memory elements along the selected word line of the read array.

References Cited (Backward Citations)

US3406659A Cited
US3624621A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-10-03 1976-04-03 1976-10-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-10-03 1980-04-03 1980-10-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-10-03 1984-04-03 1984-10-03 $7700.00 Window Closed / Lapsed

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