Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
249 words
A signal-processing system including in combination: a cyclic recorder having a plurality of parallel record tracks with associated record and readback circuits and including signal-processing operations means effecting different time delays in the respective track circuits, a first set of said tracks constructed to record and reproduce signals in a substantially linear manner, a second set of said tracks having associated record/readback circuits for recording and reproducing signals as a succession of signal-state changes, timing means including frequency control means for generating timing signals of a predetermined frequency, timing recording means receiving said timing signals and recording same on a timing track in said cyclic recorder whenever any recording operations are performed in either of said sets of tracks, a signal analyzer responsive to the predetermined signal condition and supplying an event signal, readback coNtrol means effecting readback of said timing track for actuating said timing means to provide timing signals in accordance with the frequency reproduced from said timing track and further operative to effect selective readback of signals from any of said tracks in said sets and when so selecting, said readback control means including programmable timing delay means receiving said timing pulses from said timing means and supplying a synchronization signal delayed in accordance with the signal delay in the record/reproduce circuits of the track being read out, and utilization means jointly responsive to the signal being read from said track and to said delay synchronization signal to provide a real-time indication of said recorded signal.
Claim 2
Dependent Claim
249 words
A signal-processing system including in combination: a cyclic recorder having a plurality of parallel record tracks with associated record and readback circuits and including signal-processing operations means effecting different time delays in the respective track circuits, a first set of said tracks constructed to record and reproduce signals in a substantially linear manner, a second set of said tracks having associated record/readback circuits for recording and reproducing signals as a succession of signal-state changes, timing means including frequency control means for generating timing signals of a predetermined frequency, timing recording means receiving said timing signals and recording same on a timing track in said cyclic recorder whenever any recording operations are performed in either of said sets of tracks, a signal analyzer responsive to the predetermined signal condition and supplying an event signal, readback coNtrol means effecting readback of said timing track for actuating said timing means to provide timing signals in accordance with the frequency reproduced from said timing track and further operative to effect selective readback of signals from any of said tracks in said sets and when so selecting, said readback control means including programmable timing delay means receiving said timing pulses from said timing means and supplying a synchronization signal delayed in accordance with the signal delay in the record/reproduce circuits of the track being read out, and utilization means jointly responsive to the signal being read from said track and to said delay synchronization signal to provide a real-time indication of said recorded signal.
Claim 3
Dependent Claim
68 words
The system set forth in claim 1 wherein two of said tracks in said second set of tracks for recording high-frequency signals as a signal transition in a first one of said tracks followed by a signal transition in a second one of said tracks and said record/reproduce circuit means being switchable to effect said operation or to record in said tracks independent of one of the other.
Claim 4
Dependent Claim
219 words
The system set forth in claim 2 wherein said input switching means comprises a pair of switches actuable between first and second positions and in said first position, said switches coupling first and second terminals to a record track, a third switch selectively connecting said first or second terminal to a second switching circuit, trigger means in a first switching circuit responsive to two signal-state changes to provide one signal-state change output and having an output connected to said second position of said first switch and said second switching means including inverting means connected to said third switch for receiving signals from said first terminal and inverting same and circuit means responsive to the output of said inverter means for supplying one signal-state change for two signal-state changes received and connected to said second switching means second position, and output switching means connected to both said tracks and including fourth switching means selectively connecting the output of said first track to a first position and/or to a second position, latch and binary trigger means having a trigger input connected to said second position of said fourth switch and a set input connected to said second position of said fourth switch and switching means selectively connecting the output signals of said second track to the reset inputs of said latch.
Claim 5
Dependent Claim
77 words
The system set forth in claim 1 including input switching means interposed between a set of input terminals and said record circuits for said second set of tracks, sequence control means responsive to rotations of said cyclic memory for initiating a series of recording phases, and said input switch being responsive to successive ones of said recording phases to selectively switch input signals received over a terminal to succeeding pairs of tracks in said set of tracks.
Claim 6
Dependent Claim
264 words
The system set forth in claim 1 including a selector having a plurality of control arrays of crossed insulated conductors which are interconnectable for providing a crosspoint program set of connections, a ring counter supplying actuating signals to conductors in one coordinate of two of said arrays in accordance with the signal state of said ring, input switching means selectively connecting a set of input terminals to one of said tracks in said second set and a second switching means selectively connecting the output signals of said tracks to said control means and a second output switch connecting said tracks in said first set to a single line, demodulator means for converting the outputs of said output switch to another form for supplying a signal through said control means, crossing conductors to said first coordinate in said first array connected to the ring counter being selectively connectable to said input switch for selectively connecting input terminals To one of said tracks in said second set in accordance with the programs set forth in said array and a second set of crossing conductors selectively connectable to the first conductors in said second array for controlling said output switches in accordance with the program interconnections therein, a third set of coordinate arrays having preprogrammed time delays therein in accordance with numerical significances and selectively gated in accordance with said second array connections for supplying numerical indications of delays of any track actuated in said output switches, and said timing means being responsive to said numerical signals to delay said sync signal a time in accordance therewith.
Claim 7
Dependent Claim
84 words
The system set forth in claim 5 event signal, further including an event track on said cyclic memory receiving said event signal from said signal analyzer for recording and said timing means receiving said event signal from said cyclic memory during readback of any of said tracks and generating a synchronization signal based upon said event signal as a time reference including delay means for selectively supplying a sync signal in time synchronism with any portion of any signal recorded in said cyclic memory.
Claim 8
Dependent Claim
232 words
A signal processing system including in combination: a cyclic recorder having a plurality of parallel record tracks with associated recorded readback circuits and including signal processing means exhibiting different signal delays in respective circuits associated with said tracks; a set of said tracks having associated circuits constructed to record and reproduce signals in substantially linear manner; timing means including frequency control means for generating timing signals of a predetermined frequency; timing recording means receiving said timing signals and whenever any recording operations are performed in said set of tracks, recording same on a timing track in said cyclic recorder; readback control means effecting signal readback from said timing track for actuating said timing means to provide timing signals in accordance with the frequency reproduced from said timing track and operative to effect readback from one track in said set of tracks; programmable timing delay means controlled by said readback control means and receiving said timing pulses for supplying a synchronizing signal delayed in accordance with a delay in the record/reproduce circuits of the track being read out from; and means jointly responsive to the linear signal being read from said track and to the delayed synchronizing signal to provide a real-time linear indication of the reproduce signal having a time base substantially similar to the time base of the signal before recording, which is independent of velocity variations of said cyclic recorder.
Claim 9
Dependent Claim
232 words
A signal processing system including in combination: a cyclic recorder having a plurality of parallel record tracks with associated recorded readback circuits and including signal processing means exhibiting different signal delays in respective circuits associated with said tracks; a set of said tracks having associated circuits constructed to record and reproduce signals in substantially linear manner; timing means including frequency control means for generating timing signals of a predetermined frequency; timing recording means receiving said timing signals and whenever any recording operations are performed in said set of tracks, recording same on a timing track in said cyclic recorder; readback control means effecting signal readback from said timing track for actuating said timing means to provide timing signals in accordance with the frequency reproduced from said timing track and operative to effect readback from one track in said set of tracks; programmable timing delay means controlled by said readback control means and receiving said timing pulses for supplying a synchronizing signal delayed in accordance with a delay in the record/reproduce circuits of the track being read out from; and means jointly responsive to the linear signal being read from said track and to the delayed synchronizing signal to provide a real-time linear indication of the reproduce signal having a time base substantially similar to the time base of the signal before recording, which is independent of velocity variations of said cyclic recorder.