Fail-safe time delay relay

Claim 1

A fail-safe solid state time element relay circuit to prevent relay energization and pickup where there has been an open circuit condition during the timing cycle, said time element relay having in combination, a. an externally controlled direct current voltage source, b. solid state relay energization control means, c. a predetermined time delay voltage storage means electrically connected to said solid state relay energization control means, d. a relay electrically connected to said solid state relay energization control means, e. a pulse source means for said time delay voltage storage means, f. a safety voltage storage means electrically connected to said direct current voltage source and to said pulse source means, said pulse source means electrically connected to said safety voltage storage means and said predetermined time delay storage means, said pulse source means electrically coupled to said relay to offset the charge of said predetermined time delay storage means in the event that said direct current voltage source should be momentarily disconnected from the remainder of said time element relay circuit to thereby ensure that there would not be a relay actuation before the end of said predetermined time delay, said safety voltage storage means storing energy from said direct current voltage source to thereby provide a standby reference voltage to said solid state relay energization control means, g. an excess voltage drainoff means for said predetermined time delay voltage storage means electrically connected to said predetermined time delay voltage storage means, h. reference voltage control means electrically connected to said solid state relay energization control means, i. a bypass means for said solid state relay energization control means and said reference voltage control means, said bypass means electrically connected to said direct current voltage source and controlled by said relay to provide a bypass circuit to maintain said relay energized.