Associative memory device and system

Claim 2

An associative memory cell for comparing an applied binary bit to a binary bit stored in said cell and for providing an output signal indicative of the correlation of said binary bits, comprising, in combination: first and second semiconductor memory devices each having electrically controllable first and second threshold voltage levels and each having an input electrode, an output electrode and a control electrode; means for setting the threshold voltage of said semiconductor memory devices to complementary ones of said voltage levels indicative of the state of the binary bit to be stored in said memory cell; input means for applying complementary signals to the input electrodes of said semiconductor memory devices indicative of the state of the applied binary bit to be compared to said stored binary bit; means connecting said output electrodes of said semiconductor memory devices to an output node; means for applying an interrogation signal to said control electrodes of said semiconductor memory devices; and means for obtaining an output signal from said output node indicative of the correlation of said stored bit and said applied bit at the time of application of said interrogation signal.

Claim 3

The memory cell of claim 1 in which said semiconductor memory devices each comprises an insulated gate field-effect transistor having a layer of dielectric material which exhibits non-volatile memory characteristics in response to electric fields applied thereacross and said means for setting said threshold voltages comprises means for applying an electric field of predetermined value to said layer of dielectric material.

Claim 4

The memory cell of claim 2 in which said layer of dielectric material includes a layer of silicon nitride.

Claim 5

The memory cell of claim 3 in which said layer of dielectric material comprises a layer of silicon nitride and a layer of silicon dioxide.

Claim 6

The memory cell of claim 1 which further comprises controlled switch means connected between said output electrodes of said semiconductor memory devices and said output node.

Claim 7

The memory cell of claim 5 in which said controlled switch means comprises a first semiconductor switch connected between said output electrode of said first semiconductor memory device and said output node and a second semiconductor switch connected between said output electrode of said second semiconductor memory device and said output node.

Claim 8

The memory cell of claim 6 which further comprises a resistive load for connecting said output node to a source of electrical power.

Claim 9

The memory cell of claim 7 in which said semiconductor memory devices each comprises an insulated gate field-effect transistor having a layer of dielectric material which exhibits non-volatile memory characteristics in response to electric fields applied thereacross and said means for setting said threshold voltages comprises means for applying an electric field of predetermined value to said layer of dielectric material.

Claim 10

The memory cell of claim 8 in which said layer of dielectric material includes a layer of silicon nitride.

Claim 11

The memory cell of claim 9 in which said layer of dielectric material comprises a layer of silicon nitride and a layer of silicon dioxide.

Claim 12

The memory cell of claim 10 in which each of said semiconductor switches comprises a metal-oxide-silicon insulated gate field-effect transistor.

Claim 13

An associative memory system for comparing an applied N bit binary signal to M stored binary words of N bits each and for providing output signals indicative of the correlation of said applied signal with said stored words, comprising, in combination: an M by N array of memory cells in which each row of N memory cells represents one word of N bit length and each column of M memory cells represents the same bit in each of the M words; each of said memory cells comprising: first and second semiconductor memory devices each having electrically controllable first and second threshold voltages and each having an input electrode, an output electrode and a control electrode; an output node and means connecting said output electrodes to said output node; means interconnecting the input electrodes of said first semiconductor memory devices in all of said memory cells which are in the same column; means interconnecting the input electrodes of said second semiconductor memory devices in all of said memory cells which are in the same column; means interconnecting the control electrodes of said semiconductor memory devices in all of said memory cells which are in the same row; means for setting the threshold voltage of said first and second semiconductor memory devices in each of said memory cells to complementary ones of said voltage levels indicative of the state of the binary bit to be stored in that particular memory cell; input means for applying complementary signals to the input electrodes of said first and second semiconductor memory devices of each column of memory cells indicative of the state of the respective bit of the applied binary signal to be compared with said stored binary work; means for applying an interrogation signal to said control electrodes of said semiconductor memory devices in each row of said memory cells; and means for obtaining an output signal from said output nodes in each row of said memory cells indicative of the correlation of the binary word stored in that row and the applied binary signal at the time of application of said interrogation signal.

Claim 14

An associative memory system for comparing an applied N bit binary signal to M stored binary words of N bits each and for providing output signals indicative of the correlation of said applied signal with said stored words, comprising, in combination: an M by N array of memory cells in which each row of N memory cells represents one word of N bit length and each column of M memory cells represents the same bit in each of the M words; each of said memory cells comprising: first and second semiconductor memory devices each having electrically controllable first and second threshold voltages and each having an input electrode, an output electrode and a control electrode; an output node and means connecting said output electrodes to said output node; means interconnecting the input electrodes of said first semiconductor memory devices in all of said memory cells which are in the same column; means interconnecting the input electrodes of said second semiconductor memory devices in all of said memory cells which are in the same column; means interconnecting the control electrodes of said semiconductor memory devices in all of said memory cells which are in the same row; means for setting the threshold voltage of said first and second semiconductor memory devices in each of said memory cells to complementary ones of said voltage levels indicative of the state of the binary bit to be stored in that particular memory cell; input means for applying complementary signals to the input electrodes of said first and second semiconductor memory devices of each column of memory cells indicative of the state of the respective bit of the applied binary signal to be compared with said stored binary work; means for applying an interrogation signal to said control electrodes of said semiconductor memory devices in each row of said memory cells; and means for obtaining an output signal from said output nodes in each row of said memory cells indicative of the correlation of the binary word stored in that row and the applied binary signal at the time of application of said interrogation signal.

Claim 15

The memory system of claim 12 in which said semiconductor memory devices in said memory cells each comprises an insulated gate field-effect transistor having a layer of dielectric material which exhibits non-volatile memory characteristics in response to electric fields applied thereacross and said means for setting said threshold voltages comprises means for applying an electric field of predetermined value to said layer of dielectric material.

Claim 16

The memory system of claim 13 in which said layer of dielectric material includes a layer of silicon nitride.

Claim 17

The memory system of claim 14 in which said layer of dielectric material comprises a layer of silicon nitride and a layer of silicon dioxide.

Claim 18

The memory system of claim 12 in which each of said memory cells further comprise controlled switch means connected between said output electrodes of said semiconductor memory devices and said output node.

Claim 19

The memory system of claim 6 in which said controlled switch means comprises a first semiconductor switch connected between said output electrode of said first semiconductor memory device and said output node and a second semiconductor switch connected between said output electrode of said second semiconductor memory device and said output node.

Claim 20

The memory system of claim 17 in which each of said memory cells further comprises a resistive load for connecting said output node to a source of electrical power.

Claim 21

The memory system of claim 18 in which said means for obtaining an output signal from said output nodes in each row of said memory cells comprises a series connection of a plurality of AND gates each associated with a respective memory cell in said row and which receives as its first input a signal from said output node in its respective memory cell and as its second input the output signal from the AND gate associated with the preceding memory cell in said row.

Claim 22

The memory system of claim 19 in Which said means for obtaining an output signal further comprises a plurality of semiconductor switches each associated with a respective one of said AND gates for controllably grounding the output terminals of said AND gates.

Claim 23

The memory system of claim 20 in which said semiconductor memory devices in said memory cells each comprises an insulated gate field-effect transistor having a layer of dielectric material which exhibits non-volatile memory characteristics in response to electric fields applied thereacross and said means for setting said threshold voltages comprises means for applying an electric field of predetermined value to said layer of dielectric material.

Claim 24

The memory system of claim 21 in which said layer of dielectric material includes a layer of silicon nitride.

Claim 25

The memory system of claim 22 in which said layer of dielectric material comprises a layer of silicon nitride and a layer of silicon dioxide.

Claim 26

The memory system of claim 23 in which each of said semiconductor switches comprises a metal-oxide-silicon insulated gate field-effect transistor.