Data recovery timing control circuit

Claim 2

A data block bit sequence detector comprising first retriggerable one-shot multivibrator means responsive to the presence of a data bit for generating at its output a pulse of a width dependent upon the magnitude of a control signal applied to a control terminal thereof, second re-triggerable one-shot multivibrator means for generating at its output a pulse responsive to the application of a trigger signal thereto, means for continuously applying trigger signals to said second multivibrator means only in the absence of a pulse at the output of said first multivibrator means, and means responsive to the presence and absence of a pulse at the output of said second multivibrator means for controlling the magnitude of the control signal applied to said control terminal of said first multivibrator means.

Claim 3

A data block bit sequence detector in accordance with claim 1 wherein the width of the pulse generated by said first multivibrator means is T1A seconds in the presence of a pulse at the output of said second multivibrator means and is T1B seconds in the absence of a pulse at the output of said second multivibrator means, and the width of the pulse generated by said second multivibrator means is T2 seconds, where T2 is greater than T1B and T1B is greater than T1A.

Claim 4

A data bit sequence detector comprising first circuit means having two states; said first circuit means normally being in a first state, being responsive to a data bit for switching to a second state, and normally remaining in said second state for T1A seconds after the last data bit; second circuit means having two states; said second circuit means normally being in a first state; means for placing said second circuit means in a second state responsive to said first circuit means being in its first state, said second circuit means thereafter remaining in its second state until said first circuit means has been switched to and remained in its second state for T2 seconds; and means responsive to said second circuit means being in its first state for causing said first circuit means to remain in its second state for T1B seconds rather than T1A seconds after the last data bit.

Claim 5

A data bit sequence detector comprising first circuit means having two states; said first circuit means normally being in a first state, being responsive to a data bit for switching to a second state, and normally remaining in said second state for T1A seconds after the last data bit; second circuit means having two states; said second circuit means normally being in a first state; means for placing said second circuit means in a second state responsive to said first circuit means being in its first state, said second circuit means thereafter remaining in its second state until said first circuit means has been switched to and remained in its second state for T2 seconds; and means responsive to said second circuit means being in its first state for causing said first circuit means to remain in its second state for T1B seconds rather than T1A seconds after the last data bit.

Claim 6

A data bit sequence detector in accordance with claim 3 wherein T2 is greater than T1B and T1B is greater than T1A.

Claim 7

A data bit sequence detector comprising first and second re-triggerable one-shot multivibrator means, said first multivibrator means being responsive to a data bit for generating at its output a first pulse of a width dependent upon the presence or absence of a pulse at the output of said second multivibrator means, said second multivibrator means being operative to generate a second pulse at its output which begins at the trailing edge of said first pulse and terminates after a predetermined time interval has elapsed following the leading edge of said first pulse.

Claim 8

A data bit sequence detector comprising first and second re-triggerable one-shot multivibrator means, said first multivibrator means being responsive to a data bit for generating at its output a first pulse of a width dependent upon the presence or absence of a pulse at the output of said second multivibrator means, said second multivibrator means being operative to generate a second pulse at its output which begins at the trailing edge of said first pulse and terminates after a predetermined time interval has elapsed following the leading edge of said first pulse.

Claim 9

A data bit sequence detector in accordance with claim 5 wherein the absence of a pulse at the output of said second multivibrator means controls the width of the pulse generated by said first multivibrator means to be greater than the width of the pulse generated by said first multivibrator means in the presence of a pulse at the output of said second multivibrator means.

Claim 10

A data bit sequence detector in accordance with claim 6 wherein the shorter of the two pulse widths generated by said first multivibrator means is related to the normal rate of the data bits, said predetermined time interval is related to the time interval during which data bits should be detected at a normal rate to indicate the start of a data block, and the longer of the two pulse widths generated by said first multivibrator means is related to the time interval during which no data bit should be detected to indicate the end of a data block.

Claim 11

A data bit sequence detector in accordance with claim 5 wherein the shorter of the two pulse widths generated by said first multivibrator means is related to the normal rate Of the data bits, said predetermined time interval is related to the time interval during which data bits should be detected at a normal rate to indicate the start of a data block, and the longer of the two pulse widths generated by said first multivibrator means is related to the time interval during which no data bit should be detected to indicate the end of a data block.

Claim 12

A data bit sequence detector comprising first re-triggerable one-shot multivibrator means responsive to the presence of a data bit for generating at its output a first signal of predetermined duration, second re-triggerable one-shot multivibrator means for generating at its output a second signal of greater duration, and means for continuously applying trigger pulses to said second one-shot multivibrator means only in the absence of said first signal at the output of said first one-shot multivibrator means.

Claim 13

A data bit sequence detector comprising first re-triggerable one-shot multivibrator means responsive to the presence of a data bit for generating at its output a first signal of predetermined duration, second re-triggerable one-shot multivibrator means for generating at its output a second signal of greater duration, and means for continuously applying trigger pulses to said second one-shot multivibrator means only in the absence of said first signal at the output of said first one-shot multivibrator means.

Claim 14

A data bit sequence detector in accordance with claim 9 further including means responsive to the absence of said second signal at the output of said second one-shot multivibrator means for indicating the presence of a data bit sequence.

Claim 15

A data bit sequence detector in accordance with claim 10 wherein the predetermined duration of said first signal exceeds the normal time interval between successive data bits, and the time interval between successive trigger pulses is less than the duration of said first signal.

Claim 16

A data bit sequence detector in accordance with claim 9 wherein the predetermined duration of said first signal exceeds the normal time interval between successive data bits, and the time interval between successive trigger pulses is less than the duration of said first signal.

Claim 17

A data bit sequence detector comprising first means for maintaining a first signal at its output as long as successive data bits are received within a first predetermined time interval, means connected to said first means for generating trigger pulses at a pre-set rate only in the absence of said first signal at the output of said first means, and second means connected to said trigger pulse generating means for maintaining a second signal at its output as long as successive trigger pulses are generated within a second predetermined time interval.

Claim 18

A data bit sequence detector comprising first means for maintaining a first signal at its output as long as successive data bits are received within a first predetermined time interval, means connected to said first means for generating trigger pulses at a pre-set rate only in the absence of said first signal at the output of said first means, and second means connected to said trigger pulse generating means for maintaining a second signal at its output as long as successive trigger pulses are generated within a second predetermined time interval.

Claim 19

A data bit sequence detector in accordance with claim 13 further including means connected to said second means and responsive to the absence of said second signal at the output of said second means for indicating the presence of a data bit sequence.

Claim 20

A data bit sequence detector in accordance with claim 14 wherein said second predetermined time interval exceeds said first predetermined time interval.

Claim 21

A data bit sequence detector in accordance with claim 15 wherein said trigger pulses, when generated, occur at intervals shorter than said first predetermined time interval.

Claim 22

A data bit sequence detector in accordance with claim 16 further including means connected to said second means and responsive to the absence of said second signal at the output of said second means for extending said first predetermined time interval.

Claim 23

A data bit sequence detector in accordance with claim 15 further including means connected to said second means and responsive to the absence of said second signal at the output of said second means for extending said first predetermined time interval.

Claim 24

A data bit sequence detector in accordance with claim 13 wherein said second predetermined time interval exceeds said first predetermined time interval.

Claim 25

A data bit sequence detector in accordance with claim 19 wherein said trigger pulses, when generated, occur at intervals shorter than said first predetermined time interval.

Claim 26

A data bit sequence detector in accordance with claim 20 further including means connected to said second means and responsive to the absence of said second signal at the output of said second means for extending said first predetermined time interval.

Claim 27

A data bit sequence detector in accordance with claim 13 further including means connected to said second means and responsive to the absence of said second signal at the output of said second means for extending said first predetermined time interval.