US3693097A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate control apparatus for setting the input signal counting interval
Assignee: HP Inc
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Filing: 1970-09-04
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Granted: 1972-09-19
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Expires: 1990-09-04
Abstract
Abstract A decade counting and displaying assembly are combined with a reference frequency source, pulse shaper, gate control apparatus and conventional logic elements to provide a frequency measuring device that automatically determines a time interval during which the frequency of an input signal is counted. The same components are used to provide a multiperiod averaging device that automatically determines a number of periods an input signal is to be averaged.
Inventors
- 👤 Ian T Band
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:19
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02; G01R23/10; G04; G04F; G04F10/00; G04F10/04
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
354 words
Selective timing means comprising: logic means to divide an input signal by ''''B'''', having a reset input for setting said logic means to an initial state in response to a signal being applied thereto, a drive input for altering said initial state by one count in response to each signal pulse being applied thereto and having a first output for producing signals representing a number stored in said logic means, a second output for producing a true level signal in response to the logic means being in a first cycle of operation, a third output for producing a true level signal in response to said logic means being in the initial state and a carry output for producing a signal in response to a number B being stored in said logic means, wherein B is an integer greater than 1 and said first cycle of operation begins upon a signal being applied to the reset input of said logic means and ends when a number B of signal pulses have been applied to the drive input of said logic means; decoder means having an input connected to the first output of said logic means and having an output for producing a true level signal in response to a signal representing a number ''''A'''' appearing at said input, wherein A is an integer greater than 0 and less than or equal to B-1; first gating means having an input connected to the output of said decoder means, an input connected to the second output of said logic means and having an outpUt for producing a true level signal in response to a number A being stored in said logic means during the first cycle of operation of said logic means; and second gating means having an input connected to the output of said first gating means, an input connected to the third output of said logic means and having an output for producing a true level signal in response to either the logic means being in an initial state or a number A being stored in said logic means during said first cycle of operation.
Claim 2
Dependent Claim
354 words
Selective timing means comprising: logic means to divide an input signal by ''''B'''', having a reset input for setting said logic means to an initial state in response to a signal being applied thereto, a drive input for altering said initial state by one count in response to each signal pulse being applied thereto and having a first output for producing signals representing a number stored in said logic means, a second output for producing a true level signal in response to the logic means being in a first cycle of operation, a third output for producing a true level signal in response to said logic means being in the initial state and a carry output for producing a signal in response to a number B being stored in said logic means, wherein B is an integer greater than 1 and said first cycle of operation begins upon a signal being applied to the reset input of said logic means and ends when a number B of signal pulses have been applied to the drive input of said logic means; decoder means having an input connected to the first output of said logic means and having an output for producing a true level signal in response to a signal representing a number ''''A'''' appearing at said input, wherein A is an integer greater than 0 and less than or equal to B-1; first gating means having an input connected to the output of said decoder means, an input connected to the second output of said logic means and having an outpUt for producing a true level signal in response to a number A being stored in said logic means during the first cycle of operation of said logic means; and second gating means having an input connected to the output of said first gating means, an input connected to the third output of said logic means and having an output for producing a true level signal in response to either the logic means being in an initial state or a number A being stored in said logic means during said first cycle of operation.
Claim 3
Dependent Claim
70 words
Apparatus as in claim 1 and including: a third gating means having an input connected to the output of said second gating means, an input connected to the drive input of said logic means and having a gated output for producing an output signal pulse in response to A+1 and nB+1 signal pulses appearing at the drive input of said logic means wherein n is an integer 0 or greater.
Claim 4
Dependent Claim
52 words
Apparatus as in claim 1 and including: a third gating means having a first input connected to the output of said second gating means and a second input and having a gated output for producing a signal at said output in response to true level signals at said first and second inputs.
Claim 5
Dependent Claim
185 words
Gate control apparatus comprising: a plurality of apparatus as in claim 3, each of which forms a single stage of said gate control apparatus; means connecting together the reset inputs of each stage to simultaneously set each stage to an initial state upon a signal being applied at any reset input; means connecting the drive input of a first stage to the second input of the third gating means of that first stage; means connecting the carry output of a preceding stage to the drive input of a succeeding stage; means connecting the gated output of the third gating means of a preceding stage to the second input of the third gating means of a succeeding stage for producing a signal at the gated output of a last stage of said gate control apparatus in response to AB0+1, AB1+1 . . . ABx 1+1 and nBx+1 signal pulses applied at the signal input of the first stage of said gate control apparatus, where x is an integer representing the number of stages in said gate control apparatus and n is an integer 0 or greater.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-19 | 1976-03-20 | 1976-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-19 | 1980-03-20 | 1980-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-19 | 1984-03-20 | 1984-09-19 | $7700.00 | Window Closed / Lapsed |