US3692944A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scanning circuits
Assignee: International Standard Electric Corp
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Filing: 1970-03-31
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Granted: 1972-09-19
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Expires: 1990-03-31
Abstract
Abstract Scanning circuits are provided in a time multiplex central switching exchange. Scanning involves detecting new calls, to which high priority is given, and also changes of state in previously received information. Two memories are used to store the results of scanning and each memory is divided into two parts, one for each priority level. The messages giving new calls and other changes are sent to the processor when requested by the processor.
Inventors
- 👤 Bernard Pierre Durteste
- 👤 Michel Andre Robert Henrion
- 👤 Jean-Pierre Le Corre
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:54
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
365 words
A time division multiplex data switching system controlled by a central data processing machine, the said switching system comprising a switching network, a plurality of inlets connected to a first plurality of junctors for coupling a group of trunks to the switching network, said first plurality of junctors including means for making a series-parallel conversion of signals received over a first plurality of the inlets, means coupled to make a parallel-series conversion of signals from the switching network to a second plurality of inlets, said junctors including circuits for detection and interpretation of the signals received over said first plurality of inlets, said junctors each including a signalling memory circuit in which are stored for each channel of a group of signals the expected signalling state and the indication of change or of the lack of change of state of signalling with respect to the expected state, a second plurality of junctors connected to outlets of the switching network, each of said second plurality of junctors including four memories including a data memory, a time path memory and two space path memories intended for establishing a connection between two channels, means coupling said memories to be updated by the data processing machine in relation to the communications in course, a clock circuit for supplying cyclic signals, circuits associated with said signalling memories to enable detection each time the channels processed receive a call or change their states, a sequential circuit enabling the determination of the time and space coordinates of a calling channel or of a channel changing its state, said sequential circuit including means for scanning for new calls and other changes of state and means for first determining the coordinates of the calling channels and in storing them in a first memory, means for determining thereafter the coordinates of the channels changing their states and in storing them in a second memory, means for scanning once again the new calls and means for writing their coordinates in a third memory, means for scanning once more the other changes of state and means for writing their coordinates in a fourth memory, and means for starting again the operations described hereabove in the same order.
Claim 2
Dependent Claim
365 words
A time division multiplex data switching system controlled by a central data processing machine, the said switching system comprising a switching network, a plurality of inlets connected to a first plurality of junctors for coupling a group of trunks to the switching network, said first plurality of junctors including means for making a series-parallel conversion of signals received over a first plurality of the inlets, means coupled to make a parallel-series conversion of signals from the switching network to a second plurality of inlets, said junctors including circuits for detection and interpretation of the signals received over said first plurality of inlets, said junctors each including a signalling memory circuit in which are stored for each channel of a group of signals the expected signalling state and the indication of change or of the lack of change of state of signalling with respect to the expected state, a second plurality of junctors connected to outlets of the switching network, each of said second plurality of junctors including four memories including a data memory, a time path memory and two space path memories intended for establishing a connection between two channels, means coupling said memories to be updated by the data processing machine in relation to the communications in course, a clock circuit for supplying cyclic signals, circuits associated with said signalling memories to enable detection each time the channels processed receive a call or change their states, a sequential circuit enabling the determination of the time and space coordinates of a calling channel or of a channel changing its state, said sequential circuit including means for scanning for new calls and other changes of state and means for first determining the coordinates of the calling channels and in storing them in a first memory, means for determining thereafter the coordinates of the channels changing their states and in storing them in a second memory, means for scanning once again the new calls and means for writing their coordinates in a third memory, means for scanning once more the other changes of state and means for writing their coordinates in a fourth memory, and means for starting again the operations described hereabove in the same order.
Claim 3
Dependent Claim
43 words
A data switching central exchange according to claim 1 including means by which the coordinates of the new calls or of the other changes of state contained in the memory are transmitted towards the data processing machine upon the request of this latter.
Claim 4
Dependent Claim
36 words
A data switching central exchange according to claim 1 in which the scanning may be interrupted at a time slot by the data processing machine and re-started at the same time slot t''x of another cycle.
Claim 5
Dependent Claim
36 words
A data central exchange according to claim 1, including means transmitting coordinates towards the data proCessing machine, after which scanning concerns once again the new calls the coordinates of which are stored in the first memory.
Claim 6
Dependent Claim
49 words
A data switching central exchange according to claim 1, including masks employing codes which enable the masks to take into account new calls and other changes of state coming from certain groups of channels which are supplied by the data processing machine and are written in a fifth memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-19 | 1976-03-20 | 1976-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-19 | 1980-03-20 | 1980-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-19 | 1984-03-20 | 1984-09-19 | $7700.00 | Window Closed / Lapsed |