Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
112 words
A programmer for reading a control signal from a recording medium and applying it to an output circuit comprising: means for detecting the control signal from the recording medium; means responsive to said detected control signals for generating a series of pulses of a predetermined number related to the control signal; a shift register; a control circuit responsive to said detected signal for generating a re-set signal and a register signal; means for applying said re-set signal to said shift register for enabling said shift register to receive said series of pulses and generate an output signal; means responsive to said register signal for applying said output signal to said output circuit.
Claim 2
Dependent Claim
112 words
A programmer for reading a control signal from a recording medium and applying it to an output circuit comprising: means for detecting the control signal from the recording medium; means responsive to said detected control signals for generating a series of pulses of a predetermined number related to the control signal; a shift register; a control circuit responsive to said detected signal for generating a re-set signal and a register signal; means for applying said re-set signal to said shift register for enabling said shift register to receive said series of pulses and generate an output signal; means responsive to said register signal for applying said output signal to said output circuit.
Claim 3
Dependent Claim
150 words
The programmer according to claim 1 including: means for switching said programmer to a writing mode of operation and vice versa, means for de-energizing said detecting means, energizing said pulse generating means to generate pulses, and energizing said control circuit to generate said re-set and register signals when said switching means sets said programmer in the reading mode of operation; means for presetting said shift register to count a predetermined number of pulses from said pulse generating means; said shift register responsive to said re-set signal and generating an output signal upon receiving said predetermined number of pulses; means responsive to said output signal for bleeding said pulse generating means and thereby limiting the number of pulses being generated by said pulse generating means to said predetermined member; and means for encoding said predetermined number of pulses into the control signals and writing said control signal on said recording medium.
Claim 4
Dependent Claim
29 words
The programmer according to claim 2 wherein: said register signal responsive means is adapted to apply said output signal to said output circuit during the writing mode of operation.
Claim 5
Dependent Claim
115 words
The programmer according to claim 1, including detecting means and said pulse generating means for introducing a time delay to the output pulses of said pulse generating means; said control circuit having active circuit means for providing said re-set and register signals respectively, and a passive network interposed between said detecting means and said active means for introducing time delays to said re-set and register signals so that said re-set signal is applied to said shift register while said control signal is being detected by said detecting means and that said register signal is generated after said re-set signal is extinguished but before the last of said pulses generated by said pulse generating means extinguishes.
Claim 6
Dependent Claim
69 words
The programmer according to claim 4 wherein transistors connected in series, said first transistor providing said re-set signal, said second transistor providing said register signal; and said passive network including a capacitor for storing the signal from said detecting means, and a potentiometer for controlling the time duration of the storage, whereby said active network is held operative while said control signal is being detected by said detecting means.
Claim 7
Dependent Claim
68 words
The programmer according to claim 5, wherein: said shift register includes a plurality of counters; said register incluDes a plurality of registering circuits each being interposed between a corresponding one of said counters and the output of said second transistor of said control circuit; and means for energizing the registering circuit corresponding to a particular one of said counters for applying the output thereof to the output circuit.
Claim 8
Dependent Claim
45 words
The programmer according to claim 2 wherein said bleeding means includes an active element interposed between said pulse generating means, said active element becoming operative during the writing mode of operation in response to said output signal after said predetermined number of pulses are generated.
Claim 9
Dependent Claim
26 words
The programmer according to claim 7, wherein: said bleeding circuit includes a potentiometer and a capacitor for controlling the response speed of said pulse generating means.
Claim 10
Dependent Claim
60 words
The programmer according to claim 2, wherein said encoding means includes: a Schmitt trigger responsive to the output of said pulse generating means for reshaping the output thereof into rectangular pulse waves, an a.c. generator responsive to said rectangular waves for generating bursts of a.c. waves of a particular frequency, number of bursts corresponding to the number of said pulses.
Claim 11
Dependent Claim
70 words
The programmer according to claim 9, including an erasing means having an active element responsive to the actuation of said Schmitt trigger and generating a d.c. voltage at the end of each pulse as detected by said trigger, and means for applying said d.c. voltage on said recording medium during the writing cycle of operation between successive ones of said pulses in erasing the extraneous signal on said recording medium.