Abstract A train of regularly recurring clock pulses of cadence fk 2n md, with m > OR = n, is fed to an n-stage binary frequency divider generating at its various stage outputs a set of square waves whose fundamental frequencies are subharmonically related to that cadence. Selective combination of the original clock pulses with one or more of these square waves, at least one of them in negated form, by means of different NAND gates yields sequences of short equispaced pulses recurring at these subharmonic frequencies in mutually staggered relationship; thus, a superposition of all or less than all of these pulse sequences by means of OR gates produces up to 2n-1 N regular and irregular pulse groupings each recurring at the lowest subharmonic frequency fk/2n 2md, the number K of pulses in these groupings ranging between 1 and N. Upon further subdivision by m cascaded flip-flops, there is obtained a final square wave of mean fundamental frequency Kd whose pulses may vary in length by only a small fraction of a cycle, depending upon the magnitude of m, and which may be frequency-modulated by the selective suppression of one or more constituent pulse sequences supplied to the corresponding OR gate.
Inventors
👤 Enrico Cicognani
👤 Evangelo Lyghounis
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-30 20:32
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/02; H04L5/06
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
329 words
A system for the simultaneous generation of several frequency-modulated pulse trains for multichannel telecommunication, comprising: a source of clock pulses recurring at a fixed cadence fk; a first binary frequency divider with n cascaded stages connected to receive the train of clock pulses from said source for deriving therefrom a set of square waves of different fundamental frequencies subharmonically related to said fixed cadence, said square waves being available at respective outputs of said n stages; a plurality of coincidence gates connected to receive different combinations of square waves from said outputs with said train of clock pulses from said source for deriving therefrom respective pulse sequences each with a pulse width substantially equal to that of said clock pulses and with a recurrence rate equal to the fundamental frequency of the longest square wave received by the corresponding coincidence gate, said pulse sequences being mutually staggered; logical circuitry including a set of OR gates for selectively combining certain of said pulse sequences to derive therefrom up to N different pulse groupings all recurring identically with a repetition frequency of fk/2n, N having a maximum value of 2n-1, the number K of pulses in said groupings being different for each grouping and ranging between 1 and N, said logical circuitry further including gating means in the input of each OR gate connected to be traversed by at least one relatively low-rate pulse sequence while being bypassed by at least one relatively high-rate pulse sequence in noncoincident relationship with said low-rate pulse sequence; high-speed telegraphic keying means connected to said gating means for selectively suppressing said relatively low-rate pulse sequence in the input of any OR gate to produce an alternation between two different pulse trains; and a second binary frequency divider with m cascaded stages for each of said groupings connected to convert same into an alternation of two final square waves of different but substantially constant keying frequencies centered on a mean fundamental frequency equal to Kfk/2n m.
Claim 2
Independent Claim
329 words
A system for the simultaneous generation of several frequency-modulated pulse trains for multichannel telecommunication, comprising: a source of clock pulses recurring at a fixed cadence fk; a first binary frequency divider with n cascaded stages connected to receive the train of clock pulses from said source for deriving therefrom a set of square waves of different fundamental frequencies subharmonically related to said fixed cadence, said square waves being available at respective outputs of said n stages; a plurality of coincidence gates connected to receive different combinations of square waves from said outputs with said train of clock pulses from said source for deriving therefrom respective pulse sequences each with a pulse width substantially equal to that of said clock pulses and with a recurrence rate equal to the fundamental frequency of the longest square wave received by the corresponding coincidence gate, said pulse sequences being mutually staggered; logical circuitry including a set of OR gates for selectively combining certain of said pulse sequences to derive therefrom up to N different pulse groupings all recurring identically with a repetition frequency of fk/2n, N having a maximum value of 2n-1, the number K of pulses in said groupings being different for each grouping and ranging between 1 and N, said logical circuitry further including gating means in the input of each OR gate connected to be traversed by at least one relatively low-rate pulse sequence while being bypassed by at least one relatively high-rate pulse sequence in noncoincident relationship with said low-rate pulse sequence; high-speed telegraphic keying means connected to said gating means for selectively suppressing said relatively low-rate pulse sequence in the input of any OR gate to produce an alternation between two different pulse trains; and a second binary frequency divider with m cascaded stages for each of said groupings connected to convert same into an alternation of two final square waves of different but substantially constant keying frequencies centered on a mean fundamental frequency equal to Kfk/2n m.
Claim 3
Dependent Claim
11 words
A system as defined in claim 1 wherein m > n.
Claim 4
Dependent Claim
30 words
A system as defined in claim 1 wherein at least some of the stages of said frequency divider have paired outputs with relative signal inversion connected to different coincidence gates.
Claim 5
Dependent Claim
56 words
A system as defined in claim 1 wherein said gating means includes a plurality of AND gates feeding a common OR gate, said switch means comprising a key for selectively energizing a lead with a noninverting branch connected to certain of said AND gates and with an inverting branch connected to other of said AND gates.
Claim 6
Dependent Claim
14 words
A system as defined in claim 1 wherein said coincidence gates are NAND gates.