Receiver for omega navigation system

Claim 2

A receiver responsive to a plurality of received signals of predetermined frequency, each of which is transmitted from a different location for a discrete period of time, comprising means for generating a signal, detection means operative in response to said generated signal and each of said received signals to produce an output representing the phase difference therebetween, and register means controlled by said output to store an indication commensurate with the magnitude of the phase difference of each of said plurality of signals relative to said generated signal, said register means being operative on a time sharing basis and registering a particular indication only during reception of the relevant signal of said plurality of received signals.

Claim 3

A receiver as defined in claim 1, including storage means, said storage means being coupled to said register means and being operative to store the indications commensurate with the magnitude of the phase differences of said plurality of received signals relative to said generated signal, during the period said received signals are not being received.

Claim 4

A receiver as defined in claim 1, including further register means responsive to said output to store an indication commensurate with the rate at which the receiver is moving relative to the location from which each of said plurality of signals is transmitted.

Claim 5

A receiver as defined in claim 3, including storage means, said storage means being coupled to said further register means and being operative to store the indications commensurate with the rates at which the receiver is moving relative to the locations from which each of said plurality of received signals is being transmitted, during the period said received signals are not being received.

Claim 6

A receiver as defined in claim 1, in combination with means responsive to said output for modifying said indications by an amount commensurate with the movement of the receiver relative to the locations from which said received signals are transmitted.

Claim 7

A receiver as defined in claim 1, including visual means for displaying data corresponding to the indications developed in response to selected ones of said received signals.

Claim 8

A receiver as defined in claim 1, wherein said detection means includes gate generating means responsive to said generated signal to produce a gate pulse recurring at said predetermined frequency, said gate generating means being controlled by said register means to adjust the phase of said gate pulse in accordance with the indication stored in said register means.

Claim 9

A receiver as defined in claim 1, wherein said detector means includes digitally operating gate generating means responsive to said generated signal to produce a gate pulse recurring at said predetermined frequency; said detector means being operative to produce one of three discrete signals indicating that a received signal is leading, in phase, or lagging said gate pulse, respectively; and said register means comprises digital circuitry storing indications in numerical form, and is operative in response to said discrete signals to increase said indications when said discrete signals indicate a leading condition, decrease said indications when said discrete signals indicate a lagging condition, and leave said indications unchanged when said discrete signals indicate an in phase condition; said gate generating means being controlled by said register means to change the phase of said gate pulse in increments corresponding to the numerical changes in said indications.

Claim 10

A receiver as defined in claim 8, including: digital storage means, said storage means being coupled to said register means and being operative to store said indications commensurate with the phase differences of each of said plurality of received signals, during the period said signals are not being received.

Claim 11

A receiver as defined in claim 8, in combination with further digital means responsive to the output of said detector means and operative to store indications in numerical form commensurate with the rates at which the receiver is moving relative to the locations from which each of said plurality of received signals are transmitted.

Claim 12

A receiver as defined in claim 10, in combination with means for modifying the indications in said register means in accordance with the indications stored in said further digital means.

Claim 13

A receiver as defined in claim 8, wherein said gate generating means is a digital adder.

Claim 14

A receiver as defined in claim 12, wherein said generated signal has a frequency in excess of said predetermined frequency and is applied to said digital adder to cyclically increase the count therein with a period corresponding to the period of said predetermined frequency.

Claim 15

A receiver as defined in claim 13, wherein said register means is a digital adder having the output thereof coupled to modify the count of said gate generating means in direct relation to the count appearing in said register means.

Claim 16

A receiver responsive to a plurality of received signals of predetermined frequency, each of which is transmitted from a different location for a discrete period of time, comprising means for generating a signal; first digital adder means responsive to said generated signal to produce a gate pulse recurring at said predetermined frequency; detector means responsive to each of said received signals and said gate pulse to produce one of three discrete signals indicating that a received signal is leading, in phase, or lagging said gate pulse; second digital adder means responsive to said discrete signals to increase the indication stored therein when said discrete signals indicate a leading condition, to decrease the indication stored therein when said discrete signals indicate a lagging condition, and to leave the indication stored therein when said discrete signals indicate an in-phase condition; third digital adder means responsive to said discrete signals to increase the indication stored therein when said discrete signals indicate a leading condition, to decrease the indication stored therein when said discrete signals indicate a lagging condition, and to leave the indication stored therein when said discrete signals indicate an in-phase condition; means coupling an output representing the indication stored in said second digital adder means to said first digital adder means, whereby the phase of said gate pulse is moved by an amount commensurate to the magnitude of said indication; and means controlled by said third digital adder means for modifying the indication stored in said second digital adder means in accordance with the magnitude of the indication stored in said third digital adder means.

Claim 17

A receiver responsive to a plurality of received signals of predetermined frequency, each of which is transmitted from a different location for a discrete period of time, comprising means for generating a signal; first digital adder means responsive to said generated signal to produce a gate pulse recurring at said predetermined frequency; detector means responsive to each of said received signals and said gate pulse to produce one of three discrete signals indicating that a received signal is leading, in phase, or lagging said gate pulse; second digital adder means responsive to said discrete signals to increase the indication stored therein when said discrete signals indicate a leading condition, to decrease the indication stored therein when said discrete signals indicate a lagging condition, and to leave the indication stored therein when said discrete signals indicate an in-phase condition; third digital adder means responsive to said discrete signals to increase the indication stored therein when said discrete signals indicate a leading condition, to decrease the indication stored therein when said discrete signals indicate a lagging condition, and to leave the indication stored therein when said discrete signals indicate an in-phase condition; means coupling an output representing the indication stored in said second digital adder means to said first digital adder means, whereby the phase of said gate pulse is moved by an amount commensurate to the magnitude of said indication; and means controlled by said third digital adder means for modifying the indication stored in said second digital adder means in accordance with the magnitude of the indication stored in said third digital adder means.

Claim 18

A receiver as defined in claim 15, including: a first shift register coupled to said second digital adder means; means for transferring the indications developed in said second digital adder means for each received signal, to said first shift register after the transmission period of each received signal and for retransferring said indications back to said second digital adder means during the transmission period of the corresponding received signal; a second shift register coupled to said third digital adder means; and means for transferring the indications developed in said third digital adder means for each received signal to said second shift register after the transmission period of each received signal and for retransferring said indications back to said third digital adder means during the transmission period of the corresponding received signal.