US3689845A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for suppressing interferences in a receiver of electrical signals
Assignee: US Philips Corp
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Filing: 1970-10-21
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Granted: 1972-09-05
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Expires: 1990-10-21
Abstract
Abstract A circuit arrangement for interference suppression in which the signal is applied through a gating circuit blocked during interference to a storage capacitor which maintains the signal level constant during interference. To reduce the distortion, pulses are added to the signal thus obtained, which pulses occur after releasing the gating circuit and whose amplitude is proportional to the signal step occurring as a result of the release in the output signal of the gating circuit.
Inventors
- 👤 Gerard Hepp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:42
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G3/345
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
197 words
A circuit for eliminating noise from a composite signal containing information and noise component signals, said circuit comprising means coupled to receive said composite signal for detecting said noise signal; a first pulse shaper means coupled to said noise detecting means for supplying gating pulses during the occurrance of said noise signals; a gate having an input coupled to receive said composite signal, a control input coupled to receive said gating pulses, and an output means; a storage capacitor coupled to said output means, the voltage across said capacitor being said information signal with voltage steps at the termination of said gating pulses; a second pulse shaper means coupled to said first shaper for supplying output pulses respectively starting at the termination of said gating pulses; means having inputs coupled to said second shaper and said storage capacator respectively for modulating the amplitude of said second shaper output pulses proportional to said respective voltage steps; and means for combining said information signal having voltage steps and said modulation means output pulses to produce an output signal, whereby the distortion of said information signal due to said voltage steps is substantially eliminated in said combining means output signal.
Claim 2
Dependent Claim
197 words
A circuit for eliminating noise from a composite signal containing information and noise component signals, said circuit comprising means coupled to receive said composite signal for detecting said noise signal; a first pulse shaper means coupled to said noise detecting means for supplying gating pulses during the occurrance of said noise signals; a gate having an input coupled to receive said composite signal, a control input coupled to receive said gating pulses, and an output means; a storage capacitor coupled to said output means, the voltage across said capacitor being said information signal with voltage steps at the termination of said gating pulses; a second pulse shaper means coupled to said first shaper for supplying output pulses respectively starting at the termination of said gating pulses; means having inputs coupled to said second shaper and said storage capacator respectively for modulating the amplitude of said second shaper output pulses proportional to said respective voltage steps; and means for combining said information signal having voltage steps and said modulation means output pulses to produce an output signal, whereby the distortion of said information signal due to said voltage steps is substantially eliminated in said combining means output signal.
Claim 3
Dependent Claim
43 words
A circuit as claimed in claim 1 wherein said modulating means comprises a second gate circuit having an input coupled in series with said storage capacitor, a cOntrol input coupled to said second pulse shaper, and an output coupled to said combining means.
Claim 4
Dependent Claim
41 words
A circuit as claimed in claim 1 wherein said combining means comprises a first impedance means coupled to said first gate output, a second impedance means coupled to said modulator, and a deemphasis capacitor coupled to both of said impedance means.
Claim 5
Dependent Claim
41 words
A circuit as claimed in claim 3 wherein each of said impedance means has a value such as to substantially eliminate transient effects in the output signal of said combining means after the duration of said second pulse shaper output pulses,
Claim 6
Dependent Claim
28 words
A circuit as claimed in claim 3 wherein said first and second impedance means comprise a matrix circuit means for reducing errors in said combining means output signal.
Claim 7
Dependent Claim
20 words
A circuit as claimed in claim 5 wherein said second impedance means has a tap coupled to said deemphasis capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-05 | 1976-03-06 | 1976-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-05 | 1980-03-06 | 1980-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-05 | 1984-03-06 | 1984-09-05 | $7700.00 | Window Closed / Lapsed |